[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M7EXRFGK7EFB5AYNETSHWB6Z":3,"skill-same:01M7EXRFGK7EFB5AYNETSHWB6Z":75},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":19,"linkOnly":20,"markdownContent":21,"markdownBody":22,"frontMatter":23,"refName":33,"commitSha":34,"skillDirectory":35,"forksCount":14,"repositoryHtmlUrl":36,"repositoryHomepageUrl":6,"ownerHtmlUrl":37,"ownerBlogUrl":6,"ownerDescription":6,"updatedAt":38,"install":39,"resources":52},"01M7EXRFGK7EFB5AYNETSHWB6Z","embedded-systems",null,"Use when developing firmware for microcontrollers, implementing RTOS applications, or optimizing power consumption. Invoke for STM32, ESP32, FreeRTOS, bare-metal, power optimization, real-time systems, configure peripherals, write interrupt handlers, implement DMA transfers, debug timing issues.","ibada0410\u002FCLAUDE-SKILLS","ibada0410","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F237597776?v=4","01M7EQWAZNCZV6Y4AGVBXWV5CD","Ibad Ahmed","01M7EQWB08BHXD7VT182EBQDCF",0,"MIT","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fembedded-systems\u002FSKILL.md",[],[],"2026-11-15 14:19:17",false,"---\nname: embedded-systems\ndescription: Use when developing firmware for microcontrollers, implementing RTOS applications, or optimizing power consumption. Invoke for STM32, ESP32, FreeRTOS, bare-metal, power optimization, real-time systems, configure peripherals, write interrupt handlers, implement DMA transfers, debug timing issues.\nlicense: MIT\nmetadata:\n  author: https:\u002F\u002Fgithub.com\u002FJeffallan\n  company: https:\u002F\u002Fsynergetic.solutions\n  version: \"1.1.0\"\n  domain: specialized\n  triggers: embedded systems, firmware, microcontroller, RTOS, FreeRTOS, STM32, ESP32, bare metal, interrupt, DMA, real-time\n  role: specialist\n  scope: implementation\n  output-format: code\n  related-skills: \n---\n\n# Embedded Systems Engineer\n\nSenior embedded systems engineer with deep expertise in microcontroller programming, RTOS implementation, and hardware-software integration for resource-constrained devices.\n\n## Core Workflow\n\n1. **Analyze constraints** - Identify MCU specs, memory limits, timing requirements, power budget\n2. **Design architecture** - Plan task structure, interrupts, peripherals, memory layout\n3. **Implement drivers** - Write HAL, peripheral drivers, RTOS integration\n4. **Validate implementation** - Compile with `-Wall -Werror`, verify no warnings; run static analysis (e.g. `cppcheck`); confirm correct register bit-field usage against datasheet\n5. **Optimize resources** - Minimize code size, RAM usage, power consumption\n6. **Test and verify** - Validate timing with logic analyzer or oscilloscope; check stack usage with `uxTaskGetStackHighWaterMark()`; measure ISR latency; confirm no missed deadlines under worst-case load; if issues found, return to step 4\n\n## Reference Guide\n\nLoad detailed guidance based on context:\n\n| Topic | Reference | Load When |\n|-------|-----------|-----------|\n| RTOS Patterns | `references\u002Frtos-patterns.md` | FreeRTOS tasks, queues, synchronization |\n| Microcontroller | `references\u002Fmicrocontroller-programming.md` | Bare-metal, registers, peripherals, interrupts |\n| Power Management | `references\u002Fpower-optimization.md` | Sleep modes, low-power design, battery life |\n| Communication | `references\u002Fcommunication-protocols.md` | I2C, SPI, UART, CAN implementation |\n| Memory & Performance | `references\u002Fmemory-optimization.md` | Code size, RAM usage, flash management |\n\n## Constraints\n\n### MUST DO\n- Optimize for code size and RAM usage\n- Use `volatile` for hardware registers and ISR-shared variables\n- Implement proper interrupt handling (short ISRs, defer work to tasks)\n- Add watchdog timer for reliability\n- Use proper synchronization primitives\n- Document resource usage (flash, RAM, power)\n- Handle all error conditions\n- Consider timing constraints and jitter\n\n### MUST NOT DO\n- Use blocking operations in ISRs\n- Allocate memory dynamically without bounds checking\n- Skip critical section protection\n- Ignore hardware errata and limitations\n- Use floating-point without hardware support awareness\n- Access shared resources without synchronization\n- Hardcode hardware-specific values\n- Ignore power consumption requirements\n\n## Code Templates\n\n### Minimal ISR Pattern (ARM Cortex-M \u002F STM32 HAL)\n\n```c\n\u002F* Flag shared between ISR and task — must be volatile *\u002F\nstatic volatile uint8_t g_uart_rx_flag = 0;\nstatic volatile uint8_t g_uart_rx_byte = 0;\n\n\u002F* Keep ISR short: read hardware, set flag, exit *\u002F\nvoid USART2_IRQHandler(void) {\n    if (USART2->SR & USART_SR_RXNE) {\n        g_uart_rx_byte = (uint8_t)(USART2->DR & 0xFF); \u002F* clears RXNE *\u002F\n        g_uart_rx_flag = 1;\n    }\n}\n\n\u002F* Main loop or RTOS task processes the flag *\u002F\nvoid process_uart(void) {\n    if (g_uart_rx_flag) {\n        __disable_irq();                   \u002F* enter critical section *\u002F\n        uint8_t byte = g_uart_rx_byte;\n        g_uart_rx_flag = 0;\n        __enable_irq();                    \u002F* exit critical section  *\u002F\n        handle_byte(byte);\n    }\n}\n```\n\n### FreeRTOS Task Creation Skeleton\n\n```c\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n\n#define SENSOR_TASK_STACK  256   \u002F* words *\u002F\n#define SENSOR_TASK_PRIO   2\n\nstatic QueueHandle_t xSensorQueue;\n\nstatic void vSensorTask(void *pvParameters) {\n    TickType_t xLastWakeTime = xTaskGetTickCount();\n    const TickType_t xPeriod  = pdMS_TO_TICKS(10); \u002F* 10 ms period *\u002F\n\n    for (;;) {\n        \u002F* Periodic, deadline-driven read *\u002F\n        uint16_t raw = adc_read_channel(ADC_CH0);\n        xQueueSend(xSensorQueue, &raw, 0); \u002F* non-blocking send *\u002F\n\n        \u002F* Check stack headroom in debug builds *\u002F\n        configASSERT(uxTaskGetStackHighWaterMark(NULL) > 32);\n\n        vTaskDelayUntil(&xLastWakeTime, xPeriod);\n    }\n}\n\nvoid app_init(void) {\n    xSensorQueue = xQueueCreate(8, sizeof(uint16_t));\n    configASSERT(xSensorQueue != NULL);\n\n    xTaskCreate(vSensorTask, \"Sensor\", SENSOR_TASK_STACK,\n                NULL, SENSOR_TASK_PRIO, NULL);\n    vTaskStartScheduler();\n}\n```\n\n### GPIO + Timer-Interrupt Blink (Bare-Metal STM32)\n\n```c\n\u002F* Demonstrates: clock enable, register-level GPIO, TIM2 interrupt *\u002F\n#include \"stm32f4xx.h\"\n\nvoid TIM2_IRQHandler(void) {\n    if (TIM2->SR & TIM_SR_UIF) {\n        TIM2->SR &= ~TIM_SR_UIF;           \u002F* clear update flag *\u002F\n        GPIOA->ODR ^= GPIO_ODR_OD5;        \u002F* toggle LED on PA5  *\u002F\n    }\n}\n\nvoid blink_init(void) {\n    \u002F* GPIO *\u002F\n    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;\n    GPIOA->MODER |= GPIO_MODER_MODER5_0;  \u002F* PA5 output *\u002F\n\n    \u002F* TIM2 @ ~1 Hz (84 MHz APB1 × 2 = 84 MHz timer clock) *\u002F\n    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;\n    TIM2->PSC  = 8399;   \u002F* \u002F8400  → 10 kHz  *\u002F\n    TIM2->ARR  = 9999;   \u002F* \u002F10000 → 1 Hz    *\u002F\n    TIM2->DIER |= TIM_DIER_UIE;\n    TIM2->CR1  |= TIM_CR1_CEN;\n\n    NVIC_SetPriority(TIM2_IRQn, 6);\n    NVIC_EnableIRQ(TIM2_IRQn);\n}\n```\n\n## Output Templates\n\nWhen implementing embedded features, provide:\n1. Hardware initialization code (clocks, peripherals, GPIO)\n2. Driver implementation (HAL layer, interrupt handlers)\n3. Application code (RTOS tasks or main loop)\n4. Resource usage summary (flash, RAM, power estimate)\n5. Brief explanation of timing and optimization decisions\n\nMaintained by [@jeffallan](https:\u002F\u002Fgithub.com\u002Fjeffallan), Principal Consultant at [Synergetic Solutions](https:\u002F\u002Fsynergetic.solutions)\n\n[Documentation](https:\u002F\u002Fjeffallan.github.io\u002Fclaude-skills\u002Fskills\u002Fspecialized\u002Fembedded-systems\u002F)\n","# Embedded Systems Engineer\n\nSenior embedded systems engineer with deep expertise in microcontroller programming, RTOS implementation, and hardware-software integration for resource-constrained devices.\n\n## Core Workflow\n\n1. **Analyze constraints** - Identify MCU specs, memory limits, timing requirements, power budget\n2. **Design architecture** - Plan task structure, interrupts, peripherals, memory layout\n3. **Implement drivers** - Write HAL, peripheral drivers, RTOS integration\n4. **Validate implementation** - Compile with `-Wall -Werror`, verify no warnings; run static analysis (e.g. `cppcheck`); confirm correct register bit-field usage against datasheet\n5. **Optimize resources** - Minimize code size, RAM usage, power consumption\n6. **Test and verify** - Validate timing with logic analyzer or oscilloscope; check stack usage with `uxTaskGetStackHighWaterMark()`; measure ISR latency; confirm no missed deadlines under worst-case load; if issues found, return to step 4\n\n## Reference Guide\n\nLoad detailed guidance based on context:\n\n| Topic | Reference | Load When |\n|-------|-----------|-----------|\n| RTOS Patterns | `references\u002Frtos-patterns.md` | FreeRTOS tasks, queues, synchronization |\n| Microcontroller | `references\u002Fmicrocontroller-programming.md` | Bare-metal, registers, peripherals, interrupts |\n| Power Management | `references\u002Fpower-optimization.md` | Sleep modes, low-power design, battery life |\n| Communication | `references\u002Fcommunication-protocols.md` | I2C, SPI, UART, CAN implementation |\n| Memory & Performance | `references\u002Fmemory-optimization.md` | Code size, RAM usage, flash management |\n\n## Constraints\n\n### MUST DO\n- Optimize for code size and RAM usage\n- Use `volatile` for hardware registers and ISR-shared variables\n- Implement proper interrupt handling (short ISRs, defer work to tasks)\n- Add watchdog timer for reliability\n- Use proper synchronization primitives\n- Document resource usage (flash, RAM, power)\n- Handle all error conditions\n- Consider timing constraints and jitter\n\n### MUST NOT DO\n- Use blocking operations in ISRs\n- Allocate memory dynamically without bounds checking\n- Skip critical section protection\n- Ignore hardware errata and limitations\n- Use floating-point without hardware support awareness\n- Access shared resources without synchronization\n- Hardcode hardware-specific values\n- Ignore power consumption requirements\n\n## Code Templates\n\n### Minimal ISR Pattern (ARM Cortex-M \u002F STM32 HAL)\n\n```c\n\u002F* Flag shared between ISR and task — must be volatile *\u002F\nstatic volatile uint8_t g_uart_rx_flag = 0;\nstatic volatile uint8_t g_uart_rx_byte = 0;\n\n\u002F* Keep ISR short: read hardware, set flag, exit *\u002F\nvoid USART2_IRQHandler(void) {\n    if (USART2->SR & USART_SR_RXNE) {\n        g_uart_rx_byte = (uint8_t)(USART2->DR & 0xFF); \u002F* clears RXNE *\u002F\n        g_uart_rx_flag = 1;\n    }\n}\n\n\u002F* Main loop or RTOS task processes the flag *\u002F\nvoid process_uart(void) {\n    if (g_uart_rx_flag) {\n        __disable_irq();                   \u002F* enter critical section *\u002F\n        uint8_t byte = g_uart_rx_byte;\n        g_uart_rx_flag = 0;\n        __enable_irq();                    \u002F* exit critical section  *\u002F\n        handle_byte(byte);\n    }\n}\n```\n\n### FreeRTOS Task Creation Skeleton\n\n```c\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n\n#define SENSOR_TASK_STACK  256   \u002F* words *\u002F\n#define SENSOR_TASK_PRIO   2\n\nstatic QueueHandle_t xSensorQueue;\n\nstatic void vSensorTask(void *pvParameters) {\n    TickType_t xLastWakeTime = xTaskGetTickCount();\n    const TickType_t xPeriod  = pdMS_TO_TICKS(10); \u002F* 10 ms period *\u002F\n\n    for (;;) {\n        \u002F* Periodic, deadline-driven read *\u002F\n        uint16_t raw = adc_read_channel(ADC_CH0);\n        xQueueSend(xSensorQueue, &raw, 0); \u002F* non-blocking send *\u002F\n\n        \u002F* Check stack headroom in debug builds *\u002F\n        configASSERT(uxTaskGetStackHighWaterMark(NULL) > 32);\n\n        vTaskDelayUntil(&xLastWakeTime, xPeriod);\n    }\n}\n\nvoid app_init(void) {\n    xSensorQueue = xQueueCreate(8, sizeof(uint16_t));\n    configASSERT(xSensorQueue != NULL);\n\n    xTaskCreate(vSensorTask, \"Sensor\", SENSOR_TASK_STACK,\n                NULL, SENSOR_TASK_PRIO, NULL);\n    vTaskStartScheduler();\n}\n```\n\n### GPIO + Timer-Interrupt Blink (Bare-Metal STM32)\n\n```c\n\u002F* Demonstrates: clock enable, register-level GPIO, TIM2 interrupt *\u002F\n#include \"stm32f4xx.h\"\n\nvoid TIM2_IRQHandler(void) {\n    if (TIM2->SR & TIM_SR_UIF) {\n        TIM2->SR &= ~TIM_SR_UIF;           \u002F* clear update flag *\u002F\n        GPIOA->ODR ^= GPIO_ODR_OD5;        \u002F* toggle LED on PA5  *\u002F\n    }\n}\n\nvoid blink_init(void) {\n    \u002F* GPIO *\u002F\n    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;\n    GPIOA->MODER |= GPIO_MODER_MODER5_0;  \u002F* PA5 output *\u002F\n\n    \u002F* TIM2 @ ~1 Hz (84 MHz APB1 × 2 = 84 MHz timer clock) *\u002F\n    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;\n    TIM2->PSC  = 8399;   \u002F* \u002F8400  → 10 kHz  *\u002F\n    TIM2->ARR  = 9999;   \u002F* \u002F10000 → 1 Hz    *\u002F\n    TIM2->DIER |= TIM_DIER_UIE;\n    TIM2->CR1  |= TIM_CR1_CEN;\n\n    NVIC_SetPriority(TIM2_IRQn, 6);\n    NVIC_EnableIRQ(TIM2_IRQn);\n}\n```\n\n## Output Templates\n\nWhen implementing embedded features, provide:\n1. Hardware initialization code (clocks, peripherals, GPIO)\n2. Driver implementation (HAL layer, interrupt handlers)\n3. Application code (RTOS tasks or main loop)\n4. Resource usage summary (flash, RAM, power estimate)\n5. Brief explanation of timing and optimization decisions\n\nMaintained by [@jeffallan](https:\u002F\u002Fgithub.com\u002Fjeffallan), Principal Consultant at [Synergetic Solutions](https:\u002F\u002Fsynergetic.solutions)\n\n[Documentation](https:\u002F\u002Fjeffallan.github.io\u002Fclaude-skills\u002Fskills\u002Fspecialized\u002Fembedded-systems\u002F)\n",{"name":5,"license":15,"metadata":24,"description":7},{"role":25,"scope":26,"author":27,"domain":28,"company":29,"version":30,"triggers":31,"output-format":32,"related-skills":6},"specialist","implementation","https:\u002F\u002Fgithub.com\u002FJeffallan","specialized","https:\u002F\u002Fsynergetic.solutions","1.1.0","embedded systems, firmware, microcontroller, RTOS, FreeRTOS, STM32, ESP32, bare metal, interrupt, DMA, real-time","code","main","26a049c61e6bda33cca8f5e7c1fcdcd20681221f","Engineering-and-Architecture\u002Fembedded-systems","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS","https:\u002F\u002Fgithub.com\u002Fibada0410","2026-10-15 17:21:48",{"source":8,"skillName":5,"commands":40,"prompt":50,"zipAvailable":51},[41,44,47],{"tool":42,"command":43},"npx","npx skills add ibada0410\u002FCLAUDE-SKILLS --skill embedded-systems",{"tool":45,"command":46},"bunx","bunx skills add ibada0410\u002FCLAUDE-SKILLS --skill embedded-systems",{"tool":48,"command":49},"pnpm","pnpm dlx skills add ibada0410\u002FCLAUDE-SKILLS --skill embedded-systems","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fembedded-systems\u002FSKILL.md",true,[53,59,63,67,71],{"path":54,"resourceType":55,"resourceTypeDesc":56,"sizeBytes":57,"sourceHtmlUrl":58},"references\u002Fcommunication-protocols.md","REFERENCE","参考文档",11767,"https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fembedded-systems\u002Freferences\u002Fcommunication-protocols.md",{"path":60,"resourceType":55,"resourceTypeDesc":56,"sizeBytes":61,"sourceHtmlUrl":62},"references\u002Fmemory-optimization.md",10910,"https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fembedded-systems\u002Freferences\u002Fmemory-optimization.md",{"path":64,"resourceType":55,"resourceTypeDesc":56,"sizeBytes":65,"sourceHtmlUrl":66},"references\u002Fmicrocontroller-programming.md",9647,"https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fembedded-systems\u002Freferences\u002Fmicrocontroller-programming.md",{"path":68,"resourceType":55,"resourceTypeDesc":56,"sizeBytes":69,"sourceHtmlUrl":70},"references\u002Fpower-optimization.md",10862,"https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fembedded-systems\u002Freferences\u002Fpower-optimization.md",{"path":72,"resourceType":55,"resourceTypeDesc":56,"sizeBytes":73,"sourceHtmlUrl":74},"references\u002Frtos-patterns.md",8117,"https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fembedded-systems\u002Freferences\u002Frtos-patterns.md",[76,83,90,97,104,111],{"skillNo":77,"name":78,"nameZh":6,"description":79,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":80,"categories":81,"keywords":82,"publishedAt":19},"01M7EXRQQ9T83VR5ZN5M1XNYW6","engineering-skills","Index of the engineering-team skills bundle for Claude Code, Codex, Gemini CLI, Cursor, OpenClaw, and 6 more tools. Architecture, frontend, backend, QA, DevOps, security, AI\u002FML, data engineering, Playwright, Stripe, AWS, MS365 (stdlib-only Python tools). Use when browsing or choosing among engineering-team role skills — load only the one specialist SKILL.md you need, never bulk-load the bundle.","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fengineering-skills\u002FSKILL.md",[],[],{"skillNo":84,"name":85,"nameZh":6,"description":86,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":87,"categories":88,"keywords":89,"publishedAt":19},"01M7EXRKZDN3HXASN1QFGM31MZ","engineering-advanced-skills","Index of 37 advanced engineering agent skills for Claude Code, Codex, Gemini CLI, Cursor, OpenClaw. Use when browsing or choosing among the POWERFUL-tier engineering skills: agent design, RAG, MCP servers, CI\u002FCD, database design, observability, security auditing, changelog\u002Frelease automation, reliability (SLO\u002Fchaos\u002Fflags\u002Foperators), platform ops.","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fengineering-advanced-skills\u002FSKILL.md",[],[],{"skillNo":91,"name":92,"nameZh":6,"description":93,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":94,"categories":95,"keywords":96,"publishedAt":19},"01M7EXR0NZ2D6770D7388TPNWX","dotnet-core-expert","Use when building .NET 8 applications with minimal APIs, clean architecture, or cloud-native microservices. Invoke for Entity Framework Core, CQRS with MediatR, JWT authentication, AOT compilation.","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fdotnet-core-expert\u002FSKILL.md",[],[],{"skillNo":98,"name":99,"nameZh":6,"description":100,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":101,"categories":102,"keywords":103,"publishedAt":19},"01M7EXQT86HBVM10Q4CNRPT6SK","docker-development","Docker and container development agent skill and plugin for Dockerfile optimization, docker-compose orchestration, multi-stage builds, and container security hardening. Use when: user wants to optimize a Dockerfile, create or improve docker-compose configurations, implement multi-stage builds, audit container security, reduce image size, or follow container best practices. Covers build performance, layer caching, secret management, and production-ready container patterns.","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fdocker-development\u002FSKILL.md",[],[],{"skillNo":105,"name":106,"nameZh":6,"description":107,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":108,"categories":109,"keywords":110,"publishedAt":19},"01M7EXQB6M304T47M2QJ1BFVKM","django-storages-s3","Use when configuring Django to store static and media files on AWS S3 with django-storages. Invoke when working with the STORAGES setting, S3 buckets, presigned URLs, CloudFront, or boto3-backed file storage in settings.py. Configures the Django 4.2+ STORAGES dict, public\u002Fprivate custom backends, presigned GET\u002FPOST URLs, IAM policies, and S3 mocking for tests. Trigger terms: django-storages, S3, boto3, S3Boto3Storage, STORAGES, presigned URL, CloudFront, media files, collectstatic, AWS_STORAGE_BUCKET_NAME.","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fdjango-storages-s3\u002FSKILL.md",[],[],{"skillNo":112,"name":113,"nameZh":6,"description":114,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":115,"categories":116,"keywords":117,"publishedAt":19},"01M7EXPZ44FK7J0WZXAC43RR5K","django-expert","Use when building Django web applications or REST APIs with Django REST Framework. Invoke when working with settings.py, models.py, manage.py, or any Django project file. Creates Django models with proper indexes, optimizes ORM queries using select_related\u002Fprefetch_related, builds DRF serializers and viewsets, and configures JWT authentication. Trigger terms: Django, DRF, Django REST Framework, Django ORM, Django model, serializer, viewset, Python web.","https:\u002F\u002Fgithub.com\u002Fibada0410\u002FCLAUDE-SKILLS\u002Fblob\u002Fmain\u002FEngineering-and-Architecture\u002Fdjango-expert\u002FSKILL.md",[],[]]