[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M7AMYC3MWKQ2HHCR1TJS79EX":3,"skill-same:01M7AMYC3MWKQ2HHCR1TJS79EX":48},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":19,"linkOnly":20,"markdownContent":21,"markdownBody":22,"frontMatter":23,"refName":24,"commitSha":25,"skillDirectory":26,"forksCount":27,"repositoryHtmlUrl":28,"repositoryHomepageUrl":29,"ownerHtmlUrl":30,"ownerBlogUrl":31,"ownerDescription":32,"updatedAt":33,"install":34,"resources":47},"01M7AMYC3MWKQ2HHCR1TJS79EX","logic-devices-transistors-cmos-gates-and-power",null,"Use for the circuit level underneath digital logic: the two layers this subject spans, diodes, transistors used as switches, MOSFET switching behaviour, static CMOS gate construction and why the pull-up and pull-down networks are duals, sizing and drive strength, the other logic families and when they still appear, and where power actually goes in CMOS between dynamic, short-circuit and leakage. Includes the router for the whole digital logic and firmware reference.","the-vibey-project\u002Fvibey","the-vibey-project","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F329298758?v=4","01M7AJHGZ9722CTJ4JNQZVRH0Q","the vibey project","01M7AJHGZVMG2K7TGXQ6XFHVG3",5,"MIT","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fdigital-logic-and-firmware-engineering\u002Fskills\u002Flogic-devices-transistors-cmos-gates-and-power\u002FSKILL.md",[],[],"2026-11-15 14:19:17",false,"---\nname: logic-devices-transistors-cmos-gates-and-power\ndescription: \"Use for the circuit level underneath digital logic: the two layers this subject spans, diodes, transistors used as switches, MOSFET switching behaviour, static CMOS gate construction and why the pull-up and pull-down networks are duals, sizing and drive strength, the other logic families and when they still appear, and where power actually goes in CMOS between dynamic, short-circuit and leakage. Includes the router for the whole digital logic and firmware reference.\"\n---\n\n# Digital Logic and Firmware: The Two Layers, Diodes, Transistors as Switches, MOSFET Switching, Static CMOS Gates, Sizing, Logic Families, and Power in CMOS\n\n> **Part 1 of 5** of the *CMOS, Logic Gates and Firmware Engineering* reference (plugin `digital-logic-and-firmware-engineering`), covering §0–§8. Sibling skills: `logic-standard-cells-boolean-minimization-and-arithmetic` (§9–§13), `logic-sequential-timing-metastability-cdc-and-hdl` (§14–§19), `logic-firmware-boot-root-of-trust-embedded-practice-and-security` (§20–§25), `logic-reference` (§26–§31). Section numbers are shared across the set; a reference written as §N → `skill` points into that sibling skill.\n>\n> **Currency:** Boolean algebra and CMOS circuit design do not change. Two things are moving. See §26 → `logic-reference` for the Secure Boot certificate expiry, and open-source firmware and silicon roots of trust.\n\n> **⚠️ SCOPE, because this sits between existing neighbours.** ⚠️ **A semiconductor\n> reference covers device physics and fabrication; a microarchitecture reference covers how\n> gates become processors. Neither covers the two layers here: HOW TRANSISTORS BECOME\n> BOOLEAN LOGIC, and HOW A MACHINE GETS FROM POWER-ON TO AN OPERATING SYSTEM.**\n>\n> **⚠️ These are the two ends of the stack where the abstractions are built, and where they\n> most often leak.**\n>\n> **⚠️ GOTCHA** boxes mark where the textbook idealization and the real circuit diverge.\n>\n> **The three ideas that organize this document:**\n> 1. **⚠️ CMOS COMPUTES BY CONNECTING, NOT BY AMPLIFYING** (§5). **A static CMOS gate is two\n>    complementary switch networks, one connecting the output to power and one to ground,\n>    never both. Once you see this, gate construction becomes mechanical and the power\n>    behaviour becomes obvious.**\n> 2. **⚠️ TIMING IS THE REAL CONSTRAINT, NOT LOGIC** (§15 → `logic-sequential-timing-metastability-cdc-and-hdl`, §17 → `logic-sequential-timing-metastability-cdc-and-hdl`). **Getting the Boolean\n>    function right is the easy part. Setup and hold violations, clock skew and metastability\n>    are what actually make digital systems fail, and they fail intermittently.**\n> 3. **⚠️ TRUST IS A CHAIN THAT STARTS BEFORE ANY SOFTWARE RUNS** (§22 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`, §25 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`, §26 → `logic-reference`). **Every\n>    security property the OS provides rests on firmware that executed first. Firmware is\n>    the most privileged and least examined code in the machine.**\n\n---\n\n## §0. Routing\n\n| You want... | Go to |\n|---|---|\n| The two layers here | §1 |\n| **⚠️ Diodes** | **§2** |\n| Transistors as switches | §3 |\n| MOSFET switching behaviour | §4 |\n| **⚠️ Static CMOS gates** | **§5** |\n| Sizing and drive strength | §6 |\n| Other logic families | §7 |\n| **⚠️ Power in CMOS** | **§8** |\n| Standard cells | §9 → `logic-standard-cells-boolean-minimization-and-arithmetic` |\n| **⚠️ Boolean algebra** | **§10 → `logic-standard-cells-boolean-minimization-and-arithmetic`** |\n| Minimization | §11 → `logic-standard-cells-boolean-minimization-and-arithmetic` |\n| Combinational blocks | §12 → `logic-standard-cells-boolean-minimization-and-arithmetic` |\n| **⚠️ Arithmetic** | **§13 → `logic-standard-cells-boolean-minimization-and-arithmetic`** |\n| **⚠️ Latches and flip-flops** | **§14 → `logic-sequential-timing-metastability-cdc-and-hdl`** |\n| **⚠️ Timing and metastability** | **§15 → `logic-sequential-timing-metastability-cdc-and-hdl`** |\n| State machines | §16 → `logic-sequential-timing-metastability-cdc-and-hdl` |\n| **⚠️ Clock domain crossing** | **§17 → `logic-sequential-timing-metastability-cdc-and-hdl`** |\n| HDL and synthesis | §18 → `logic-sequential-timing-metastability-cdc-and-hdl` |\n| Test and DFT | §19 → `logic-sequential-timing-metastability-cdc-and-hdl` |\n| Firmware landscape | §20 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security` |\n| **⚠️ The boot sequence** | **§21 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`** |\n| **⚠️ Root of trust** | **§22 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`** |\n| ACPI and platform interfaces | §23 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security` |\n| Embedded firmware | §24 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security` |\n| **⚠️ Firmware security** | **§25 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`** |\n| **What's live** | **§26 → `logic-reference`** |\n| Misconceptions, numbers | §27–§28 → `logic-reference` |\n| Sources, quick ref, method | §29–§31 → `logic-reference` |\n\n---\n\n## §1. The Two Layers\n\n```\n⚠️ WHERE THIS FILE SITS\n   device physics ────────── a semiconductor reference\n   ⚠️ TRANSISTORS AS SWITCHES ──── §2-§4     ← here\n   ⚠️ CMOS GATES ───────────────── §5-§9     ← here\n   ⚠️ BOOLEAN LOGIC ────────────── §10-§13   ← here\n   ⚠️ SEQUENTIAL AND TIMING ────── §14-§19   ← here\n   microarchitecture ─────── a microarchitecture reference\n   ⚠️ FIRMWARE AND BOOT ────────── §20-§25   ← here\n   OS and applications ───── elsewhere\n⚠️ THE SYMMETRY WORTH NOTICING  ⚠️ both layers are ones people\n   treat as solved and invisible — and both are where the\n   hardest-to-diagnose failures live. ⚠️ A setup-time violation\n   and a firmware bug share a signature: intermittent,\n   environment-dependent, and invisible at the layer above\n```\n\n---\n\n# PART I — DEVICES AS SWITCHES\n\n## §2. ⚠️ Diodes\n\n```\n⚠️ THE BEHAVIOUR  ⚠️ conducts one way, blocks the other.\n   ⚠️ Forward drop ~0.7 V for silicon, ~0.3 V for Schottky,\n   and the exponential I-V relation means the \"0.7 V\" is a\n   convenient fiction that shifts with current\n⚠️ THE TYPES AND WHAT EACH IS FOR\n   ⚠️ SIGNAL \u002F RECTIFIER  power conversion, half and full wave\n   ⚠️ SCHOTTKY  ⚠️ low forward drop, very fast recovery, higher\n      leakage — used where switching speed or drop matters\n   ⚠️ ZENER  ⚠️ deliberately operated in REVERSE BREAKDOWN as a\n      voltage reference or clamp\n   ⚠️ TVS  ⚠️ transient voltage suppression — the ESD protection\n      part on every exposed line (see a peripherals reference §18)\n   ⚠️ LED  forward-biased emission; ⚠️ needs current limiting,\n      because the exponential I-V means a small voltage\n      increase destroys it\n   ⚠️ PHOTODIODE and solar cell — the same junction run backwards\n   ⚠️ VARACTOR  voltage-controlled capacitance, used in tuning\n⚠️ THE PRACTICAL USES THAT RECUR  ⚠️ FLYBACK\u002Ffreewheeling diode\n   across any inductive load (⚠️ a relay or motor without one\n   destroys the driving transistor) · reverse polarity\n   protection · ⚠️ diode-OR for redundant supplies · clamping ·\n   level shifting\n⚠️ ⚠️ DIODE LOGIC exists (AND\u002FOR from diodes alone) but ⚠️ CANNOT\n   INVERT and degrades the signal at every stage — which is\n   exactly why active devices are necessary for real logic\n```\n\n---\n\n## §3. Transistors as Switches\n\n**⚠️ BJT versus MOSFET**, ⚠️ **and the distinction that matters for logic:**\n```\n⚠️ BJT  ⚠️ CURRENT-controlled. Base current sets collector\n   current. ⚠️ Continuous base current means continuous power —\n   which is why bipolar logic families (TTL, ECL) burn power\n   even when idle\n⚠️ MOSFET  ⚠️ VOLTAGE-controlled via an insulated gate.\n   ⚠️ ESSENTIALLY NO DC GATE CURRENT. ⚠️ THIS IS THE PROPERTY\n   THAT MADE CMOS WIN — a gate that draws no static current can\n   be scaled to billions\n⚠️ THE MODES  cutoff (off) · ⚠️ linear\u002Ftriode (⚠️ acting as a\n   resistor — this is the SWITCH-ON region for logic) ·\n   saturation (⚠️ constant current — the AMPLIFIER region, which\n   digital design mostly passes THROUGH rather than sits in)\n⚠️ n-CHANNEL vs p-CHANNEL  ⚠️ nMOS conducts when gate is HIGH;\n   pMOS conducts when gate is LOW. ⚠️ This complementary pair is\n   the whole basis of §5\n⚠️ ⚠️ nMOS PASSES A STRONG 0 AND A WEAK 1; pMOS PASSES A STRONG 1\n   AND A WEAK 0. ⚠️ This asymmetry is not a detail — it dictates\n   which network goes where in a CMOS gate, and it is why pass\n   transistor logic needs care (§7)\n```\n\n---\n\n## §4. MOSFET Switching Behaviour\n\n**⚠️ The parasitic capacitances are the whole story of speed**: ⚠️ **gate capacitance must\nbe charged and discharged to switch the device, and everything a gate drives is capacitance\nto the driver.**\n**⚠️ Propagation delay** is therefore ⚠️ **roughly the load capacitance divided by the\navailable drive current — which is why delay depends on FANOUT and on wire length.**\n**⚠️ Rise and fall times** and ⚠️ **the danger of slow edges: a slowly-transitioning input\nleaves BOTH transistors in the receiving gate partially on, causing SHORT-CIRCUIT current\n(§8) and, at the extreme, oscillation.**\n**⚠️ The Miller effect** — ⚠️ **gate-drain capacitance appears amplified during the\ntransition, which is why the switching waveform has a plateau.**\n**⚠️ Threshold voltage, body effect, and temperature dependence** — ⚠️ **and the\nuncomfortable fact that transistors get SLOWER hot but LEAKIER hot, so the worst case for\ntiming and the worst case for power are at opposite corners.**\n**⚠️ PVT corners** (process, voltage, temperature) — ⚠️ **designs must work at all of them,\nwhich is why sign-off is done at multiple corners rather than nominal.**\n\n---\n\n# PART II — CMOS CIRCUIT DESIGN\n\n## §5. ⚠️ Static CMOS Gates\n\n> **⚠️ The single most useful construction in this file. Once you see it, you can draw any\n> logic gate from its Boolean expression mechanically.**\n```\n⚠️ THE STRUCTURE  ⚠️ every static CMOS gate is TWO NETWORKS\n   ⚠️ PULL-UP NETWORK (PUN)  ⚠️ pMOS transistors, connects output\n      to VDD\n   ⚠️ PULL-DOWN NETWORK (PDN)  ⚠️ nMOS transistors, connects\n      output to GND\n   ⚠️ THEY ARE COMPLEMENTARY AND MUTUALLY EXCLUSIVE — exactly one\n      conducts for any input combination. ⚠️ Both on = short\n      circuit; both off = floating output\n⚠️ ⚠️ THE CONSTRUCTION RULE\n   ⚠️ PDN: SERIES nMOS = AND · PARALLEL nMOS = OR\n   ⚠️ PUN: the DUAL — series becomes parallel and vice versa\n   ⚠️ The output is INHERENTLY INVERTED\n⚠️ ⚠️ THEREFORE NAND AND NOR ARE THE NATURAL GATES, and\n   ⚠️ AND and OR are MORE EXPENSIVE than NAND and NOR because\n   they are a NAND\u002FNOR followed by an inverter. ⚠️ This is\n   backwards from how people learn Boolean algebra, and it is\n   why synthesized netlists are full of NANDs\n⚠️ THE INVERTER  one pMOS, one nMOS, gates tied together —\n   ⚠️ the simplest possible instance of the pattern\n⚠️ ⚠️ NAND IS PREFERRED OVER NOR in practice, because NOR puts\n   pMOS devices in SERIES — and pMOS is intrinsically weaker\n   (lower hole mobility), so a series pMOS stack is slow (§6)\n⚠️ COMPLEX GATES  ⚠️ AOI (and-or-invert) and OAI implement\n   multi-level functions in ONE gate, which is faster and\n   smaller than composing separate gates\n⚠️ STACK HEIGHT  ⚠️ practically limited to about 3-4 series\n   devices, because series resistance and body effect compound\n```\n\n---\n\n## §6. Sizing and Drive Strength\n\n**⚠️ Why pMOS is usually wider**: ⚠️ **hole mobility is roughly 2–3× lower than electron\nmobility, so a pMOS must be proportionally wider to match an nMOS's drive.** ⚠️ **A\n\"balanced\" inverter uses that ratio; ⚠️ deliberately unbalanced sizing skews the switching\nthreshold, which is sometimes what you want.**\n**⚠️ Series stacks need upsizing** — ⚠️ **two devices in series each need roughly double\nwidth to match a single device's drive.**\n**⚠️ LOGICAL EFFORT** is the design method worth knowing: ⚠️ **it separates a gate's\nintrinsic difficulty from its load, giving a systematic way to size a path and to find the\noptimal number of stages — and the well-known result is that a fanout of roughly 4 per\nstage is near-optimal.**\n**⚠️ Buffer insertion and repeaters** — ⚠️ **driving a large load or a long wire directly is\nslow; a chain of progressively larger buffers is faster despite adding stages.**\n**⚠️ Drive strength in a cell library** (§9 → `logic-standard-cells-boolean-minimization-and-arithmetic`) is exactly this made discrete: ⚠️ **X1, X2, X4\nversions of the same logic function.**\n\n---\n\n## §7. Other Logic Families\n\n```\n⚠️ PASS TRANSISTOR LOGIC  ⚠️ fewer transistors, and ⚠️ suffers\n   the threshold drop of §3 — an nMOS pass gate delivers only\n   VDD − Vt. ⚠️ Needs level restoration\n⚠️ ⚠️ TRANSMISSION GATE  ⚠️ nMOS and pMOS in PARALLEL, gates\n   driven oppositely — ⚠️ passes BOTH levels strongly. ⚠️ The\n   standard building block for multiplexers and latches (§14)\n⚠️ DYNAMIC \u002F DOMINO LOGIC  ⚠️ precharge then evaluate, using a\n   clock. ⚠️ Faster and smaller; ⚠️ vulnerable to charge sharing,\n   leakage and noise, needs careful clocking, and is much less\n   used than it once was because leakage got worse with scaling\n⚠️ LEGACY FAMILIES worth recognizing  ⚠️ TTL (bipolar, fast for\n   its day, power-hungry) · ⚠️ ECL (very fast, never off,\n   enormous power) · ⚠️ 74-series and 4000-series CMOS, still\n   genuinely useful for learning and glue logic\n⚠️ ⚠️ LOGIC LEVELS AND INTERFACING  ⚠️ VIL\u002FVIH\u002FVOL\u002FVOH and NOISE\n   MARGIN. ⚠️ 3.3 V and 5 V and 1.8 V parts do not simply\n   interconnect — ⚠️ level shifting is required, and driving a\n   5 V-tolerant-only input from 3.3 V may not reach VIH\n⚠️ OPEN DRAIN \u002F OPEN COLLECTOR  ⚠️ needs a pull-up, gives\n   wired-AND, and is why I²C works as a multi-drop bus\n```\n\n---\n\n## §8. ⚠️ Power in CMOS\n\n```\n⚠️ ⚠️ DYNAMIC POWER  P = α · C · V² · f\n   ⚠️ α = ACTIVITY FACTOR (fraction of cycles the node switches)\n   ⚠️ THE V² TERM is why voltage scaling was the most powerful\n   lever ever available — and why its end mattered so much\n   (see a semiconductor reference §5)\n⚠️ SHORT-CIRCUIT POWER  ⚠️ during a transition BOTH networks are\n   briefly partially on. ⚠️ Small if edges are fast, and it\n   grows badly with slow edges (§4)\n⚠️ ⚠️ STATIC \u002F LEAKAGE POWER  ⚠️ subthreshold conduction, gate\n   oxide tunnelling, junction leakage. ⚠️ Negligible in old\n   processes, MAJOR in modern ones — and it rises sharply with\n   temperature, creating a THERMAL RUNAWAY risk\n⚠️ THE TECHNIQUES\n   ⚠️ CLOCK GATING  ⚠️ the highest-value one — the clock network\n      itself switches every cycle and can be a large fraction of\n      dynamic power\n   ⚠️ POWER GATING  cut supply to idle blocks, attacking leakage\n   ⚠️ MULTI-Vt  ⚠️ high-Vt cells on non-critical paths (slow,\n      low leakage), low-Vt only where speed is needed\n   ⚠️ DVFS · multiple voltage domains with level shifters ·\n      operand isolation\n⚠️ ⚠️ THE GLITCH PROBLEM  ⚠️ unbalanced path delays cause spurious\n   transitions that do real work and burn real power before\n   settling — ⚠️ a meaningful fraction of dynamic power in\n   arithmetic-heavy logic\n```\n","# Digital Logic and Firmware: The Two Layers, Diodes, Transistors as Switches, MOSFET Switching, Static CMOS Gates, Sizing, Logic Families, and Power in CMOS\n\n> **Part 1 of 5** of the *CMOS, Logic Gates and Firmware Engineering* reference (plugin `digital-logic-and-firmware-engineering`), covering §0–§8. Sibling skills: `logic-standard-cells-boolean-minimization-and-arithmetic` (§9–§13), `logic-sequential-timing-metastability-cdc-and-hdl` (§14–§19), `logic-firmware-boot-root-of-trust-embedded-practice-and-security` (§20–§25), `logic-reference` (§26–§31). Section numbers are shared across the set; a reference written as §N → `skill` points into that sibling skill.\n>\n> **Currency:** Boolean algebra and CMOS circuit design do not change. Two things are moving. See §26 → `logic-reference` for the Secure Boot certificate expiry, and open-source firmware and silicon roots of trust.\n\n> **⚠️ SCOPE, because this sits between existing neighbours.** ⚠️ **A semiconductor\n> reference covers device physics and fabrication; a microarchitecture reference covers how\n> gates become processors. Neither covers the two layers here: HOW TRANSISTORS BECOME\n> BOOLEAN LOGIC, and HOW A MACHINE GETS FROM POWER-ON TO AN OPERATING SYSTEM.**\n>\n> **⚠️ These are the two ends of the stack where the abstractions are built, and where they\n> most often leak.**\n>\n> **⚠️ GOTCHA** boxes mark where the textbook idealization and the real circuit diverge.\n>\n> **The three ideas that organize this document:**\n> 1. **⚠️ CMOS COMPUTES BY CONNECTING, NOT BY AMPLIFYING** (§5). **A static CMOS gate is two\n>    complementary switch networks, one connecting the output to power and one to ground,\n>    never both. Once you see this, gate construction becomes mechanical and the power\n>    behaviour becomes obvious.**\n> 2. **⚠️ TIMING IS THE REAL CONSTRAINT, NOT LOGIC** (§15 → `logic-sequential-timing-metastability-cdc-and-hdl`, §17 → `logic-sequential-timing-metastability-cdc-and-hdl`). **Getting the Boolean\n>    function right is the easy part. Setup and hold violations, clock skew and metastability\n>    are what actually make digital systems fail, and they fail intermittently.**\n> 3. **⚠️ TRUST IS A CHAIN THAT STARTS BEFORE ANY SOFTWARE RUNS** (§22 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`, §25 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`, §26 → `logic-reference`). **Every\n>    security property the OS provides rests on firmware that executed first. Firmware is\n>    the most privileged and least examined code in the machine.**\n\n---\n\n## §0. Routing\n\n| You want... | Go to |\n|---|---|\n| The two layers here | §1 |\n| **⚠️ Diodes** | **§2** |\n| Transistors as switches | §3 |\n| MOSFET switching behaviour | §4 |\n| **⚠️ Static CMOS gates** | **§5** |\n| Sizing and drive strength | §6 |\n| Other logic families | §7 |\n| **⚠️ Power in CMOS** | **§8** |\n| Standard cells | §9 → `logic-standard-cells-boolean-minimization-and-arithmetic` |\n| **⚠️ Boolean algebra** | **§10 → `logic-standard-cells-boolean-minimization-and-arithmetic`** |\n| Minimization | §11 → `logic-standard-cells-boolean-minimization-and-arithmetic` |\n| Combinational blocks | §12 → `logic-standard-cells-boolean-minimization-and-arithmetic` |\n| **⚠️ Arithmetic** | **§13 → `logic-standard-cells-boolean-minimization-and-arithmetic`** |\n| **⚠️ Latches and flip-flops** | **§14 → `logic-sequential-timing-metastability-cdc-and-hdl`** |\n| **⚠️ Timing and metastability** | **§15 → `logic-sequential-timing-metastability-cdc-and-hdl`** |\n| State machines | §16 → `logic-sequential-timing-metastability-cdc-and-hdl` |\n| **⚠️ Clock domain crossing** | **§17 → `logic-sequential-timing-metastability-cdc-and-hdl`** |\n| HDL and synthesis | §18 → `logic-sequential-timing-metastability-cdc-and-hdl` |\n| Test and DFT | §19 → `logic-sequential-timing-metastability-cdc-and-hdl` |\n| Firmware landscape | §20 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security` |\n| **⚠️ The boot sequence** | **§21 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`** |\n| **⚠️ Root of trust** | **§22 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`** |\n| ACPI and platform interfaces | §23 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security` |\n| Embedded firmware | §24 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security` |\n| **⚠️ Firmware security** | **§25 → `logic-firmware-boot-root-of-trust-embedded-practice-and-security`** |\n| **What's live** | **§26 → `logic-reference`** |\n| Misconceptions, numbers | §27–§28 → `logic-reference` |\n| Sources, quick ref, method | §29–§31 → `logic-reference` |\n\n---\n\n## §1. The Two Layers\n\n```\n⚠️ WHERE THIS FILE SITS\n   device physics ────────── a semiconductor reference\n   ⚠️ TRANSISTORS AS SWITCHES ──── §2-§4     ← here\n   ⚠️ CMOS GATES ───────────────── §5-§9     ← here\n   ⚠️ BOOLEAN LOGIC ────────────── §10-§13   ← here\n   ⚠️ SEQUENTIAL AND TIMING ────── §14-§19   ← here\n   microarchitecture ─────── a microarchitecture reference\n   ⚠️ FIRMWARE AND BOOT ────────── §20-§25   ← here\n   OS and applications ───── elsewhere\n⚠️ THE SYMMETRY WORTH NOTICING  ⚠️ both layers are ones people\n   treat as solved and invisible — and both are where the\n   hardest-to-diagnose failures live. ⚠️ A setup-time violation\n   and a firmware bug share a signature: intermittent,\n   environment-dependent, and invisible at the layer above\n```\n\n---\n\n# PART I — DEVICES AS SWITCHES\n\n## §2. ⚠️ Diodes\n\n```\n⚠️ THE BEHAVIOUR  ⚠️ conducts one way, blocks the other.\n   ⚠️ Forward drop ~0.7 V for silicon, ~0.3 V for Schottky,\n   and the exponential I-V relation means the \"0.7 V\" is a\n   convenient fiction that shifts with current\n⚠️ THE TYPES AND WHAT EACH IS FOR\n   ⚠️ SIGNAL \u002F RECTIFIER  power conversion, half and full wave\n   ⚠️ SCHOTTKY  ⚠️ low forward drop, very fast recovery, higher\n      leakage — used where switching speed or drop matters\n   ⚠️ ZENER  ⚠️ deliberately operated in REVERSE BREAKDOWN as a\n      voltage reference or clamp\n   ⚠️ TVS  ⚠️ transient voltage suppression — the ESD protection\n      part on every exposed line (see a peripherals reference §18)\n   ⚠️ LED  forward-biased emission; ⚠️ needs current limiting,\n      because the exponential I-V means a small voltage\n      increase destroys it\n   ⚠️ PHOTODIODE and solar cell — the same junction run backwards\n   ⚠️ VARACTOR  voltage-controlled capacitance, used in tuning\n⚠️ THE PRACTICAL USES THAT RECUR  ⚠️ FLYBACK\u002Ffreewheeling diode\n   across any inductive load (⚠️ a relay or motor without one\n   destroys the driving transistor) · reverse polarity\n   protection · ⚠️ diode-OR for redundant supplies · clamping ·\n   level shifting\n⚠️ ⚠️ DIODE LOGIC exists (AND\u002FOR from diodes alone) but ⚠️ CANNOT\n   INVERT and degrades the signal at every stage — which is\n   exactly why active devices are necessary for real logic\n```\n\n---\n\n## §3. Transistors as Switches\n\n**⚠️ BJT versus MOSFET**, ⚠️ **and the distinction that matters for logic:**\n```\n⚠️ BJT  ⚠️ CURRENT-controlled. Base current sets collector\n   current. ⚠️ Continuous base current means continuous power —\n   which is why bipolar logic families (TTL, ECL) burn power\n   even when idle\n⚠️ MOSFET  ⚠️ VOLTAGE-controlled via an insulated gate.\n   ⚠️ ESSENTIALLY NO DC GATE CURRENT. ⚠️ THIS IS THE PROPERTY\n   THAT MADE CMOS WIN — a gate that draws no static current can\n   be scaled to billions\n⚠️ THE MODES  cutoff (off) · ⚠️ linear\u002Ftriode (⚠️ acting as a\n   resistor — this is the SWITCH-ON region for logic) ·\n   saturation (⚠️ constant current — the AMPLIFIER region, which\n   digital design mostly passes THROUGH rather than sits in)\n⚠️ n-CHANNEL vs p-CHANNEL  ⚠️ nMOS conducts when gate is HIGH;\n   pMOS conducts when gate is LOW. ⚠️ This complementary pair is\n   the whole basis of §5\n⚠️ ⚠️ nMOS PASSES A STRONG 0 AND A WEAK 1; pMOS PASSES A STRONG 1\n   AND A WEAK 0. ⚠️ This asymmetry is not a detail — it dictates\n   which network goes where in a CMOS gate, and it is why pass\n   transistor logic needs care (§7)\n```\n\n---\n\n## §4. MOSFET Switching Behaviour\n\n**⚠️ The parasitic capacitances are the whole story of speed**: ⚠️ **gate capacitance must\nbe charged and discharged to switch the device, and everything a gate drives is capacitance\nto the driver.**\n**⚠️ Propagation delay** is therefore ⚠️ **roughly the load capacitance divided by the\navailable drive current — which is why delay depends on FANOUT and on wire length.**\n**⚠️ Rise and fall times** and ⚠️ **the danger of slow edges: a slowly-transitioning input\nleaves BOTH transistors in the receiving gate partially on, causing SHORT-CIRCUIT current\n(§8) and, at the extreme, oscillation.**\n**⚠️ The Miller effect** — ⚠️ **gate-drain capacitance appears amplified during the\ntransition, which is why the switching waveform has a plateau.**\n**⚠️ Threshold voltage, body effect, and temperature dependence** — ⚠️ **and the\nuncomfortable fact that transistors get SLOWER hot but LEAKIER hot, so the worst case for\ntiming and the worst case for power are at opposite corners.**\n**⚠️ PVT corners** (process, voltage, temperature) — ⚠️ **designs must work at all of them,\nwhich is why sign-off is done at multiple corners rather than nominal.**\n\n---\n\n# PART II — CMOS CIRCUIT DESIGN\n\n## §5. ⚠️ Static CMOS Gates\n\n> **⚠️ The single most useful construction in this file. Once you see it, you can draw any\n> logic gate from its Boolean expression mechanically.**\n```\n⚠️ THE STRUCTURE  ⚠️ every static CMOS gate is TWO NETWORKS\n   ⚠️ PULL-UP NETWORK (PUN)  ⚠️ pMOS transistors, connects output\n      to VDD\n   ⚠️ PULL-DOWN NETWORK (PDN)  ⚠️ nMOS transistors, connects\n      output to GND\n   ⚠️ THEY ARE COMPLEMENTARY AND MUTUALLY EXCLUSIVE — exactly one\n      conducts for any input combination. ⚠️ Both on = short\n      circuit; both off = floating output\n⚠️ ⚠️ THE CONSTRUCTION RULE\n   ⚠️ PDN: SERIES nMOS = AND · PARALLEL nMOS = OR\n   ⚠️ PUN: the DUAL — series becomes parallel and vice versa\n   ⚠️ The output is INHERENTLY INVERTED\n⚠️ ⚠️ THEREFORE NAND AND NOR ARE THE NATURAL GATES, and\n   ⚠️ AND and OR are MORE EXPENSIVE than NAND and NOR because\n   they are a NAND\u002FNOR followed by an inverter. ⚠️ This is\n   backwards from how people learn Boolean algebra, and it is\n   why synthesized netlists are full of NANDs\n⚠️ THE INVERTER  one pMOS, one nMOS, gates tied together —\n   ⚠️ the simplest possible instance of the pattern\n⚠️ ⚠️ NAND IS PREFERRED OVER NOR in practice, because NOR puts\n   pMOS devices in SERIES — and pMOS is intrinsically weaker\n   (lower hole mobility), so a series pMOS stack is slow (§6)\n⚠️ COMPLEX GATES  ⚠️ AOI (and-or-invert) and OAI implement\n   multi-level functions in ONE gate, which is faster and\n   smaller than composing separate gates\n⚠️ STACK HEIGHT  ⚠️ practically limited to about 3-4 series\n   devices, because series resistance and body effect compound\n```\n\n---\n\n## §6. Sizing and Drive Strength\n\n**⚠️ Why pMOS is usually wider**: ⚠️ **hole mobility is roughly 2–3× lower than electron\nmobility, so a pMOS must be proportionally wider to match an nMOS's drive.** ⚠️ **A\n\"balanced\" inverter uses that ratio; ⚠️ deliberately unbalanced sizing skews the switching\nthreshold, which is sometimes what you want.**\n**⚠️ Series stacks need upsizing** — ⚠️ **two devices in series each need roughly double\nwidth to match a single device's drive.**\n**⚠️ LOGICAL EFFORT** is the design method worth knowing: ⚠️ **it separates a gate's\nintrinsic difficulty from its load, giving a systematic way to size a path and to find the\noptimal number of stages — and the well-known result is that a fanout of roughly 4 per\nstage is near-optimal.**\n**⚠️ Buffer insertion and repeaters** — ⚠️ **driving a large load or a long wire directly is\nslow; a chain of progressively larger buffers is faster despite adding stages.**\n**⚠️ Drive strength in a cell library** (§9 → `logic-standard-cells-boolean-minimization-and-arithmetic`) is exactly this made discrete: ⚠️ **X1, X2, X4\nversions of the same logic function.**\n\n---\n\n## §7. Other Logic Families\n\n```\n⚠️ PASS TRANSISTOR LOGIC  ⚠️ fewer transistors, and ⚠️ suffers\n   the threshold drop of §3 — an nMOS pass gate delivers only\n   VDD − Vt. ⚠️ Needs level restoration\n⚠️ ⚠️ TRANSMISSION GATE  ⚠️ nMOS and pMOS in PARALLEL, gates\n   driven oppositely — ⚠️ passes BOTH levels strongly. ⚠️ The\n   standard building block for multiplexers and latches (§14)\n⚠️ DYNAMIC \u002F DOMINO LOGIC  ⚠️ precharge then evaluate, using a\n   clock. ⚠️ Faster and smaller; ⚠️ vulnerable to charge sharing,\n   leakage and noise, needs careful clocking, and is much less\n   used than it once was because leakage got worse with scaling\n⚠️ LEGACY FAMILIES worth recognizing  ⚠️ TTL (bipolar, fast for\n   its day, power-hungry) · ⚠️ ECL (very fast, never off,\n   enormous power) · ⚠️ 74-series and 4000-series CMOS, still\n   genuinely useful for learning and glue logic\n⚠️ ⚠️ LOGIC LEVELS AND INTERFACING  ⚠️ VIL\u002FVIH\u002FVOL\u002FVOH and NOISE\n   MARGIN. ⚠️ 3.3 V and 5 V and 1.8 V parts do not simply\n   interconnect — ⚠️ level shifting is required, and driving a\n   5 V-tolerant-only input from 3.3 V may not reach VIH\n⚠️ OPEN DRAIN \u002F OPEN COLLECTOR  ⚠️ needs a pull-up, gives\n   wired-AND, and is why I²C works as a multi-drop bus\n```\n\n---\n\n## §8. ⚠️ Power in CMOS\n\n```\n⚠️ ⚠️ DYNAMIC POWER  P = α · C · V² · f\n   ⚠️ α = ACTIVITY FACTOR (fraction of cycles the node switches)\n   ⚠️ THE V² TERM is why voltage scaling was the most powerful\n   lever ever available — and why its end mattered so much\n   (see a semiconductor reference §5)\n⚠️ SHORT-CIRCUIT POWER  ⚠️ during a transition BOTH networks are\n   briefly partially on. ⚠️ Small if edges are fast, and it\n   grows badly with slow edges (§4)\n⚠️ ⚠️ STATIC \u002F LEAKAGE POWER  ⚠️ subthreshold conduction, gate\n   oxide tunnelling, junction leakage. ⚠️ Negligible in old\n   processes, MAJOR in modern ones — and it rises sharply with\n   temperature, creating a THERMAL RUNAWAY risk\n⚠️ THE TECHNIQUES\n   ⚠️ CLOCK GATING  ⚠️ the highest-value one — the clock network\n      itself switches every cycle and can be a large fraction of\n      dynamic power\n   ⚠️ POWER GATING  cut supply to idle blocks, attacking leakage\n   ⚠️ MULTI-Vt  ⚠️ high-Vt cells on non-critical paths (slow,\n      low leakage), low-Vt only where speed is needed\n   ⚠️ DVFS · multiple voltage domains with level shifters ·\n      operand isolation\n⚠️ ⚠️ THE GLITCH PROBLEM  ⚠️ unbalanced path delays cause spurious\n   transitions that do real work and burn real power before\n   settling — ⚠️ a meaningful fraction of dynamic power in\n   arithmetic-heavy logic\n```\n",{"name":5,"description":7},"develop","ae32736a1aabddabca5d2c96d665aa0ebc7d8700","src\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fdigital-logic-and-firmware-engineering\u002Fskills\u002Flogic-devices-transistors-cmos-gates-and-power",3,"https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey","https:\u002F\u002Fthe-vibey-project.github.io\u002Fvibey\u002F","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project","https:\u002F\u002Fvibewithadam.matthewsteinberger.com","freedom for software engineers","2026-11-15 05:47:42",{"source":8,"skillName":5,"commands":35,"prompt":45,"zipAvailable":46},[36,39,42],{"tool":37,"command":38},"npx","npx skills add the-vibey-project\u002Fvibey --skill logic-devices-transistors-cmos-gates-and-power",{"tool":40,"command":41},"bunx","bunx skills add the-vibey-project\u002Fvibey --skill logic-devices-transistors-cmos-gates-and-power",{"tool":43,"command":44},"pnpm","pnpm dlx skills add the-vibey-project\u002Fvibey --skill logic-devices-transistors-cmos-gates-and-power","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fdigital-logic-and-firmware-engineering\u002Fskills\u002Flogic-devices-transistors-cmos-gates-and-power\u002FSKILL.md",true,[],[49,56,63,70,77,84],{"skillNo":50,"name":51,"nameZh":6,"description":52,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":53,"categories":54,"keywords":55,"publishedAt":19},"01M7AT1FQJAE1FQYAMDTF490Y4","white-paper-writing","Use when writing white papers, technical reports, policy documents, thought leadership pieces, or any long-form authoritative document. Triggers on requests to write, structure, outline, or review white papers, technical reports, position papers, policy briefs, or evidence-driven arguments. Also use for B2B content marketing strategy, technical documentation requiring authority, academic-style reports, or any document that must educate while persuading. Use when someone asks \"how should I structure this\" for a long-form document.","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fwriting-craft\u002Fskills\u002Fwhite-paper-writing\u002FSKILL.md",[],[],{"skillNo":57,"name":58,"nameZh":6,"description":59,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":60,"categories":61,"keywords":62,"publishedAt":19},"01M7AT16BJRJJKK2MASXRZS76G","prose-technical-mechanics","Use when editing or writing prose at a technical\u002Fmechanical level: choosing between Anglo-Saxon and Latinate diction, placing information in topic vs stress positions, writing periodic vs cumulative sentences, handling sentence rhythm, punctuation as logic, transitions, paragraph structure, or phonesthetics. Use when someone wants to understand WHY prose works or doesn't, not just surface-level style advice. Triggers on word choice, sentence structure, emphasis, rhythm, diction, or any deep writing mechanics question.","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fwriting-craft\u002Fskills\u002Fprose-technical-mechanics\u002FSKILL.md",[],[],{"skillNo":64,"name":65,"nameZh":6,"description":66,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":67,"categories":68,"keywords":69,"publishedAt":19},"01M7AT0W9HT0ZZ9Y287NW99MR3","prose-mechanics","Use when writing, editing, or analyzing prose style; when trying to avoid generic AI-sounding writing; when applying specific prose styles such as journalistic, academic, narrative, KJV biblical, Hemingway plain, Latinate\u002FJamesian, Orwellian, Augustan, Victorian, Early Modern (Bacon, Browne, Milton), or free indirect discourse; or when coaching someone on writing voice and mechanics. Triggers on any request to improve, analyze, or write in a specific prose style, to fix \"AI-sounding\" writing, to make prose more vivid or concrete, to vary sentence rhythm, or to understand how a particular writer achieves their effects.","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fwriting-craft\u002Fskills\u002Fprose-mechanics\u002FSKILL.md",[],[],{"skillNo":71,"name":72,"nameZh":6,"description":73,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":74,"categories":75,"keywords":76,"publishedAt":19},"01M7AT0KR635JX66X2X6F3E2CP","narrative-structure","Use when structuring stories, pitches, presentations, white papers, or any persuasive narrative; analyzing the hero's journey in fiction or non-fiction; applying StoryBrand for business communication; designing narrative arcs for thought leadership; or understanding Vogler, Snyder, Propp, or Campbell frameworks. Triggers on any narrative structure, storytelling, pitch structure, StoryBrand, hero's journey, three-act structure, Freytag, Save the Cat, narrative arc, or \"how should I structure this story\u002Fpitch\u002Fpresentation\" request.","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fwriting-craft\u002Fskills\u002Fnarrative-structure\u002FSKILL.md",[],[],{"skillNo":78,"name":79,"nameZh":6,"description":80,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":81,"categories":82,"keywords":83,"publishedAt":19},"01M7AT0AKGW09NKKZDYBT8VRDE","legal-brief-writing","Use when writing legal briefs, motions, or any court filing; when analyzing judicial cognition and persuasion; when applying elite brief-writing techniques from Roberts, Clement, Kagan, Garner; or when structuring legal arguments for maximum persuasion. Also use for autistic\u002Fneurodivergent advocates who need to understand how their natural communication style maps to elite legal advocacy. Triggers on any legal writing, brief drafting, motion preparation, or legal argument structuring request.","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fwriting-craft\u002Fskills\u002Flegal-brief-writing\u002FSKILL.md",[],[],{"skillNo":85,"name":86,"nameZh":6,"description":87,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":88,"categories":89,"keywords":90,"publishedAt":19},"01M7AT00VWPS4Q8B5VEMXX9NQT","journal-publishability-criteria","Use whenever a research paper, article or preprint is being written, revised, reviewed or published, and specifically before every publication of docs\u002Fpaper.md. Covers what legitimate journals actually gate on, in order of gating — the editor's desk screen (scope, novelty, package problems), what reviewers judge (methodological soundness, claims the evidence can carry, statistical and qualitative reporting), EQUATOR reporting guidelines, the ICMJE authorship criteria, COPE's view of text recycling, the near-universal generative-AI policy (no AI author, disclosure, author responsibility), TOP 2025 transparency standards, how to verify a journal is legitimate, submitting without an institution, and a pre-submission checklist. Triggers on requests to evaluate, review, prepare or submit a paper, to judge publishability, to write a declarations or data-availability section, to disclose AI use, or to check a journal.","https:\u002F\u002Fgithub.com\u002Fthe-vibey-project\u002Fvibey\u002Fblob\u002Fdevelop\u002Fsrc\u002Fvibey_tools\u002Fskills\u002Fplugins\u002Fwriting-craft\u002Fskills\u002Fjournal-publishability-criteria\u002FSKILL.md",[],[]]