[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M7A9B10CS31FYREFEPJ948B4":3,"skill-same:01M7A9B10CS31FYREFEPJ948B4":99},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":19,"linkOnly":20,"markdownContent":21,"markdownBody":22,"frontMatter":23,"refName":39,"commitSha":40,"skillDirectory":41,"forksCount":42,"repositoryHtmlUrl":43,"repositoryHomepageUrl":44,"ownerHtmlUrl":45,"ownerBlogUrl":46,"ownerDescription":47,"updatedAt":48,"install":49,"resources":62},"01M7A9B10CS31FYREFEPJ948B4","jetson-customize-clocks",null,"Use to lock\u002Fcap Jetson CPU\u002FGPU\u002FEMC clocks, toggle EMC\u002FCPU DVFS, or change cpufreq governors by editing BPMP DTB and nvpower.sh pre-flash. Do NOT use for live tuning or nvpmodel edits.","themusebook\u002Fskills","themusebook","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F349927247?v=4","01M7A5C1RV5S3V5FF6ZACVDNRN","musebook","01M7A5C1SFC3KRZAXNN60XJ7KM",0,"Apache-2.0","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002FSKILL.md",[],[],"2026-11-15 14:19:17",false,"---\nname: jetson-customize-clocks\ndescription: Use to lock\u002Fcap Jetson CPU\u002FGPU\u002FEMC clocks, toggle EMC\u002FCPU DVFS, or change cpufreq governors by editing BPMP DTB and nvpower.sh pre-flash. Do NOT use for live tuning or nvpmodel edits.\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - clocks\n    - cpu\n    - gpu\n    - emc\n    - dvfs\n    - bwmgr\n    - bpmp\n    - nvpower\n    - cpufreq\n    - devfreq\n  domain: clocks\n---\n\n# Customize Clocks\n\n## Purpose\n\nCustomize CPU, GPU, and EMC clock behavior on a Jetson target by editing files under `Linux_for_Tegra\u002F` before flashing the image. Two layers are in scope:\n\n- The **BPMP DTB** at `Linux_for_Tegra\u002Fbootloader\u002F\u003CBPFDTB_FILE>` — per-clock `max-rate-custom` ceilings, plus the EMC DVFS gate (bwmgr + cactmon on all SoCs; osp-controller on T26x only).\n- **nvpower.sh** at `Linux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh` — cpufreq \u002F devfreq governors and (optionally) per-device min \u002F max \u002F static rates written to sysfs at boot.\n\nCommon triggers: \"lock CPU\u002FGPU\u002FEMC frequency\", \"pin GPU to Fmax\", \"pin EMC to MAXN\", \"disable\u002Fenable EMC DVFS\", \"disable\u002Fenable CPU DVFS\", \"set CPU\u002FGPU max rate\", \"change cpufreq governor\".\n\nOut of scope: runtime clock tuning on a live target (no flash step), nvpmodel power-mode edits (use the sibling skill `\u002Fjetson-customize-nvpmodel`), and silicon-ceiling overrides (`max-rate-maxn` is read-only).\n\n## Prerequisites\n\nResolve the active profile per\n[`..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md`](..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md).\nRefuse and route in these cases:\n\n| Condition | Refuse with |\n|---|---|\n| No active profile, or `active: NA` | Route to `\u002Fjetson-set-target` or `\u002Fjetson-init-target`. |\n| Profile lacks `bsp_image:` block | Route to `\u002Fjetson-init-image`. |\n| `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F` missing | Route to `\u002Fjetson-init-image`. |\n| `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` missing or not a git repo | Route to `\u002Fjetson-init-source`. |\n\nResolve paths:\n\n- `\u003Cbsp_image.root_path>` from `bsp_image.root_path:` if present, else `\u003Cworkspace>\u002FImage`.\n- `\u003Csource.root_path>` from `source.root_path:` if present, else `\u003Cworkspace>\u002FSource`.\n\n`\u003Cbsp_image.root_path>` is **read-only** for this skill; every write\n(Operation 1's BPMP DTB and Operation 2's `nvpower.sh`) lands under\n`\u003Csource.root_path>` (the overlay tracker). This is the workflow\ninvariant in\n[`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants`](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants) —\nhand-editing upstream silently destroys the diff trail and makes\n`\u002Fjetson-promote-image` a noop.\n\n## Instructions\n\n1. Resolve the prerequisites above (active profile, BSP image extracted, source overlay tracker initialized).\n2. Pick the operation from the table below.\n3. Follow the linked procedure section — Operation 1 (BPMP DTB), Operation 2 (`nvpower.sh`), or the MAXN recipe for both.\n4. Commit the edit inside the overlay tracker per each Operation's commit convention.\n5. Deploy with `\u002Fjetson-promote-image` → `\u002Fjetson-flash-image`. The new BPMP DTB and `nvpower.sh` take effect on the next boot.\n\n### Supported operations\n\n| Operation | Where the edit lives | Procedure section |\n|---|---|---|\n| Lock a CPU \u002F GPU clock to a specific rate | BPMP DTB `max-rate-custom` on the clock node + `nvpower.sh` governor `performance` | \"Content edit: `max-rate-custom`\" + \"Pick the edit\" |\n| Lock EMC at its init rate (disable EMC DVFS) | BPMP DTB: `bwmgr.enabled = 0`, `cactmon.enabled = 0`, plus `\u002Fdelete-node\u002F osp-controller` on T26x only | \"Content edit: EMC DVFS disable \u002F enable\" |\n| Re-enable EMC DVFS | BPMP DTB: `bwmgr.enabled = 1`, `cactmon.enabled = 1`, restore `osp-controller` on T26x | \"Content edit: EMC DVFS disable \u002F enable\" |\n| Pin everything to MAXN for stress runs | Combine the above + nvpmodel MAXN as boot default | see Recipe |\n| Lower a clock's hard ceiling without locking | BPMP DTB `max-rate-custom` only | \"Content edit: `max-rate-custom`\" |\n| Bound a device's rate without pinning | `nvpower.sh` min\u002Fmax via sysfs | \"Pick the edit\" |\n\n## Operation 1 — BPMP DTB edits\n\nFollow the BPMP-DTB customization protocol in\n[`..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md).\nThe protocol owns the mechanics — pristine import on first touch,\n`dtc` decompile, recompile, sanity-check, commit. This skill\nsupplies only the **clock-specific content** (which nodes and\nproperties to edit during the protocol's \"Edit the DTS\" step).\n\nThe edited `.dtb` lands in the `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F`\noverlay tracker. `\u002Fjetson-promote-image`'s channel A walks the\ntracker and copies the file into `bsp_image`. **Do not edit\n`\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F\u003Cbpmp-dtb>`\ndirectly** — that's the promote output, not an input.\n\n### Resolve the SKU-correct BPMP DTB\n\nPer the protocol's \"Resolving the active BPMP DTB\" section, read\n`BPFDTB_FILE` from the active flash conf. For the common Thor \u002F\nsingle-SKU conf shapes this is the static `BPFDTB_FILE=...` line\nin the per-board `.conf` and the value is authoritative as-is.\n\nFor **SKU-multiplexed conf shapes** (Orin AGX devkit conf chain\nthat selects a different BPMP DTB per `board_sku`\u002F`board_FAB`\nvia `update_flash_args_common` — see\n[`..\u002F..\u002Fcontext\u002Fbsp-customization-software-layers.md#per-board-conf-dispatch--update_flash_args_common`](..\u002F..\u002Fcontext\u002Fbsp-customization-software-layers.md#per-board-conf-dispatch--update_flash_args_common)),\nwalk the dispatch chain with `board_sku=\u003Cmodule.sku>` and\n`board_FAB=\u003Cmodule.revision or empty>` from the active profile,\nand read `BPFDTB_FILE` from the dispatch output — **not** from\nthe static line of the per-board `.conf`. Static and dispatched\nvalues match for non-multiplexed confs; the dispatch is\nmandatory only when the conf chain conditionally overrides\n`BPFDTB_FILE`.\n\n### List effective max rates (inspection)\n\nInspect both layers of the runtime ceiling — see [`references\u002Fclock-control-model.md#effective-runtime-ceiling`](references\u002Fclock-control-model.md#effective-runtime-ceiling) — before deciding on a `max-rate-custom` value.\n\nInspection cookbook (BPMP-side decompile + grep; nvpmodel-side awk over the boot default mode) is in [`references\u002Fbpmp-dtb-clock-edits.md#inspection-cookbook`](references\u002Fbpmp-dtb-clock-edits.md#inspection-cookbook).\n\nFor the nvpmodel layer see [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md).\n\nThis step does not mutate state — it's a precondition for sizing\nthe edit in the \"Content edit: `max-rate-custom` on a named clock node\" step.\n\n### Content edit: `max-rate-custom` on a named clock node\n\nDuring the \"Edit the DTS\" step of the protocol, modify the property\ninside the named clock node — never `lateinit`. `max-rate-custom`\nmust be strictly below the clock's hard cap (`max-rate-maxn` if\ndefined, otherwise the live `max_rate` from a running target of\nthe same chip \u002F SKU).\n\nDTS edit form, semantics, and the nvpmodel ↔ BPMP clock-node\nmapping live in [`references\u002Fbpmp-dtb-clock-edits.md`](references\u002Fbpmp-dtb-clock-edits.md).\n\nThen hand control back to the protocol — its \"Recompile\", \"Sanity-check\nthe recompiled blob\", \"Stage in the overlay tracker\", and \"Cleanup\"\nsteps cover the rest.\nCommit-message convention per the protocol:\n`\u003CBPMP_BASENAME>: jetson-customize-clocks — \u003Cclock-node> max-rate-custom = \u003Cvalue>`.\n\n### Content edit: EMC DVFS disable \u002F enable\n\nDefault behavior (EMC DVFS on) requires no edit. Disabling EMC\nDVFS is a **multi-node edit** applied inside the same \"Edit the DTS\" step of\nthe protocol, **not** a `bwmgr` toggle:\n\n| # | Edit | Scope |\n|---|---|---|\n| 1 | `bwmgr.enabled = \u003C0x00>` | All SoCs, mandatory |\n| 2 | `cactmon.enabled = \u003C0x00>` | All SoCs, mandatory |\n| 3 | `\u002Fdelete-node\u002F osp-controller` | **T26x (Thor) mandatory** — T23x (Orin) has no such node, skip |\n\nDetection: `dtc -I dtb -O dts \u003Cbpmp-dtb> | grep -c osp-controller`\n— zero hits ⇒ T23x path. Full DTS snippets, the surviving-paths\nfailure modes, and the re-enable procedure are in\n[`references\u002Femc-dvfs-disable.md`](references\u002Femc-dvfs-disable.md).\n\nApply the protocol's \"Recompile\" through \"Cleanup\" steps once the multi-node edit is in\nplace. Commit-message convention:\n`\u003CBPMP_BASENAME>: jetson-customize-clocks — EMC DVFS disable (bwmgr + cactmon[+ osp-controller])`.\n\nDisabling raises idle power; intended for stress \u002F performance\ntests, not production rootfs.\n\n### Re-run + idempotency\n\nPer the protocol's \"Re-runnability\" section, re-running this\nskill with the same target value produces a no-op commit. Re-\nrunning with a different value rewrites the same property — `git\nlog -- $BPMP_REL` shows the per-run history. To return a clock\nto its `max-rate-maxn` ceiling, edit the DTS to remove the\n`max-rate-custom` line and recompile.\n\n## Operation 2 — nvpower.sh edits\n\nEdits `nvpower.sh`, which runs at boot via `nvpower.service` to set\ncpufreq \u002F devfreq governors and rates.\n\n### The per-script file\n\nThe script this Operation edits has the relative path:\n\n```\nLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh\n```\n\nIt lives in **two** roots; the Operation walks both:\n\n| Role | Location | Skill writes? |\n|---|---|---|\n| Detection + pristine source | `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002F` | no — read-only |\n| Overlay edit target + git commit | `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002F` | yes |\n\nSubsequent sub-steps refer to **the per-script file** to mean the overlay\ncopy under `\u003Csource.root_path>`. The `\u003Cbsp_image.root_path>` copy is read\nonce during the pristine-import step below, then never touched again.\n\n### Overlay edit recipe (apply before editing nvpower.sh)\n\nFollow the canonical\n[Off-skill edits recipe](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#off-skill-edits)\nin the workflow doc — pristine import + customization commit pair, both\ngated by the preview gate. `nvpower.sh` is a single file with no\npropagation set; one pristine commit + one customization commit covers\nthe entire change.\n\nConcrete substitutions for this skill:\n\n- `\u003Crel>\u002F\u003Cfile>` is `rootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`.\n- Suggested pristine-import message:\n  `import pristine: rootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`,\n  body `Source: \u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F (BSP \u003Cbsp_image.version>)`.\n- Suggested customization-commit header:\n  `jetson-customize-clocks: nvpower.sh \u003Csummary>`,\n  body lines like `set_cpufreq_governor: desired_cpufreq_gov \"schedutil\" -> \"performance\"`.\n\n### Pick the edit\n\nFunction locations (`set_cpufreq_governor`, `set_devfreq_governor`), common-edit recipes (pin to Fmax, static rate, min\u002Fmax bounds), and the `nvidia-l4t-init` package-upgrade caveat live in [`references\u002Fnvpower-sh-edits.md`](references\u002Fnvpower-sh-edits.md).\n\n### Deploy\n\nThe customization commit in the overlay tracker does not reach the device\non its own. The Deploy chain:\n\n1. **`\u002Fjetson-promote-image`** — copies every tracked file in the overlay\n   into `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F`. Diff-aware (skip\n   byte-identical); uses `sudo cp -p` for `rootfs\u002F*` destinations.\n2. **`\u002Fjetson-flash-image`** — flashes the updated `bsp_image` to the\n   device. `nvpower.service` runs the new script on the next boot.\n3. (Alternate, no flash) Copy `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`\n   directly to the running target's `\u002Fetc\u002Fsystemd\u002Fnvpower.sh`, then\n   `sudo systemctl restart nvpower.service` (or reboot).\n\nEditing `\u003Csource.root_path>\u002F...` without committing — or editing\n`\u003Cbsp_image.root_path>\u002F...` directly — does nothing for `\u002Fjetson-promote-image`\nand is silently lost on the next `\u002Fjetson-init-image` re-extract.\n\n## Recipe — pin everything to MAXN for stress \u002F performance runs\n\nCombines Operations 1 + 2. Operation 1's BPMP edits all flow\nthrough one round of the protocol (a single decompile \u002F multi-node\nedit \u002F recompile \u002F commit cycle — don't round-trip the protocol\ntwice for the same `.dtb`):\n\n1. **BPMP DTB** (the \"Content edit: `max-rate-custom` on a named clock node\" step content): leave `max-rate-custom` unset on every CPU \u002F GPU \u002F EMC clock; remove existing `max-rate-custom` lines that lower the ceiling.\n2. **BPMP DTB** (the \"Content edit: EMC DVFS disable \u002F enable\" step content): pin EMC at its init rate — `bwmgr.enabled = 0`, `cactmon.enabled = 0`, plus `\u002Fdelete-node\u002F osp-controller` on T26x (skip on T23x).\n3. Apply both content edits inside one protocol \"Edit the DTS\" invocation, then run the remaining protocol steps (recompile, sanity-check, single customization commit covering both content edits).\n4. **nvpower.sh** (Operation 2): set `desired_cpufreq_gov=\"performance\"` and `desired_devfreq_gov=\"performance\"` unconditionally; remove the GPU\u002Fnvjpg skip in `set_devfreq_governor`. Applies via Operation 2's overlay edit recipe (the \"Overlay edit recipe (apply before editing nvpower.sh)\" step) — a separate overlay-tracker pristine + customization commit pair on the rootfs script, distinct from the BPMP-DTB protocol's commit.\n5. Set the boot-default nvpmodel mode to MAXN via [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md) — the per-clock nvpmodel cap clamps below `max-rate-maxn` regardless of BPMP DTB content.\n\nDeploy [`\u002Fjetson-promote-image`](..\u002Fjetson-promote-image\u002FSKILL.md) → [`\u002Fjetson-flash-image`](..\u002Fjetson-flash-image\u002FSKILL.md) picks up the new BPMP DTB (via the overlay tracker) and the edited `nvpower.sh` (via the same overlay tracker) on the next flash.\n\n## Limitations\n\n- **Image-build-time only.** All edits land under `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` and reach the device only via `\u002Fjetson-promote-image` → `\u002Fjetson-flash-image`. Live-target tuning is out of scope.\n- **`max-rate-custom` only lowers the ceiling.** It must be strictly below `max-rate-maxn`; raising the silicon cap is not supported.\n- **Effective ceiling is two-layer.** The runtime ceiling is `min(BPMP cap, active-nvpmodel-mode cap)`. The nvpmodel cap is owned by `\u002Fjetson-customize-nvpmodel`; this skill does not edit it.\n- **SoC-conditional EMC DVFS gate.** Disabling EMC DVFS requires editing different node sets on T23x (bwmgr + cactmon) vs T26x (bwmgr + cactmon + delete `osp-controller`). Mis-detection produces undefined behavior.\n- **T23x GPU cap is multi-node.** The GPU clock is split across `nafll_gpusys` and every `nafll_gpcX`; the cap binds only when applied to all of them.\n- **`nvpower.sh` is package-managed.** It ships in `nvidia-l4t-init`; package upgrades clobber in-place edits. Long-lived setups should prefer a systemd drop-in or sibling helper.\n- **ODMDATA wins.** When an ODMDATA token covers a property, the token overrides direct BPMP DTS edits at flash time. Direct BPMP DTS edits are the fallback for properties no NVIDIA token reaches.\n- **`max-rate-maxn` and `lateinit` are off-limits.** `max-rate-maxn` is the silicon ceiling (read-only). `lateinit` is for boot-time clock init, not ceiling overrides — never touch either.\n- **BPMP DTB may be SKU-multiplexed.** On compound \u002F dispatched flash confs (Orin AGX devkit chain), `BPFDTB_FILE` is selected by `board_sku` \u002F `board_FAB` via `update_flash_args_common`. Reading the static `BPFDTB_FILE=` line is wrong when the chain conditionally overrides it; resolve via the dispatch instead.\n\n## Troubleshooting\n\n| Error | Cause | Solution |\n|---|---|---|\n| `max-rate-custom` set but clock still ramps to `max-rate-maxn` on T23x GPU | Only `nafll_gpusys` was capped; the `nafll_gpcX` partitions still run at `max-rate-maxn` and dominate the effective ceiling. | Apply the same `max-rate-custom` to `nafll_gpusys` **and** every `nafll_gpcX` node enumerated by `grep -nE '^\\s*nafll_gpc[0-9]+\\s*:' \u003Cdecompiled.dts>`. |\n| EMC DVFS disable appears to apply but EMC still scales on T26x | Only `bwmgr.enabled = \u003C0x00>` was set; `osp-controller` survives and re-issues frequency changes via the QoS path. | Add edits #2 (`cactmon.enabled = \u003C0x00>`) and #3 (`\u002Fdelete-node\u002F osp-controller`) inside the same \"Edit the DTS\" step. Verify `osp-controller` via `dtc -I dtb -O dts \u003Cbpmp-dtb> \\| grep -c osp-controller` → expect 0. |\n| EMC DVFS disable rejected on T23x with \"node not found\" for `osp-controller` | T23x (Orin) BPMP DTBs do not contain `osp-controller`; edit #3 must be skipped on T23x. | Detect SoC family with the `grep -c osp-controller` step; only apply #3 when the count is ≥1. |\n| BPMP refuses to load DTB after edit: `max-rate-custom >= max-rate-maxn` | `max-rate-custom` was set to or above the silicon ceiling. | Lower `max-rate-custom` strictly below `max-rate-maxn`. If `max-rate-maxn` is absent from the node, query the live cap on a running target: `cat \u002Fsys\u002Fkernel\u002Fdebug\u002Fbpmp\u002Fdebug\u002Fclk\u002F\u003Cclock>\u002Fmax_rate`. |\n| `osp-controller` re-appears after `status = \"disabled\"` | `status = \"disabled\"` does not remove the node from the device tree; BPMP still walks it. | Replace with `\u002Fdelete-node\u002F osp-controller;` — the node must not exist for BPMP to skip the path. |\n| Edits to `nvpower.sh` lost after `apt upgrade` | `nvpower.sh` is owned by the `nvidia-l4t-init` deb and gets overwritten on upgrade. | For long-lived test setups, package edits into a systemd drop-in or a sibling helper file referenced by `nvpower.sh`, rather than editing `nvpower.sh` in place. |\n| `\u002Fjetson-promote-image` is a no-op after editing the BPMP DTB | The edit was applied to `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F`, which is `\u002Fjetson-promote-image`'s output — not its input. | Move the edit to `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F\u003CBPFDTB_FILE>` (the overlay tracker) and commit through the BPMP-DTB protocol. |\n| Cap appears to apply on first boot then resets after a power-mode change | The active nvpmodel mode's per-clock cap clamps below `max-rate-custom`. | Inspect both layers; if nvpmodel is binding, raise (or remove) the nvpmodel cap via `\u002Fjetson-customize-nvpmodel`. The BPMP cap alone is not the runtime ceiling. |\n\n## References\n\n- [`..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md) — canonical BPMP-DTB customization protocol (pristine import, decompile, edit, recompile, sanity-check, commit). Operation 1 of this skill is a content-only consumer; the protocol owns the mechanics.\n- [`references\u002Fclock-control-model.md`](references\u002Fclock-control-model.md) — layer stack, two-ceilings overview, effective-runtime-ceiling formula.\n- [`references\u002Fbpmp-dtb-clock-edits.md`](references\u002Fbpmp-dtb-clock-edits.md) — two-ceilings semantics, DTS edit form, nvpmodel ↔ BPMP clock-node mapping, inspection cookbook.\n- [`references\u002Femc-dvfs-disable.md`](references\u002Femc-dvfs-disable.md) — full SoC-conditional EMC DVFS disable procedure with DTS snippets, detection, re-enable.\n- [`references\u002Fnvpower-sh-edits.md`](references\u002Fnvpower-sh-edits.md) — `nvpower.sh` function locations + common-edit recipes + package-upgrade caveat.\n- [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md) — sibling skill: nvpmodel power modes. The active mode's per-clock cap clamps below the BPMP DTB cap.\n","# Customize Clocks\n\n## Purpose\n\nCustomize CPU, GPU, and EMC clock behavior on a Jetson target by editing files under `Linux_for_Tegra\u002F` before flashing the image. Two layers are in scope:\n\n- The **BPMP DTB** at `Linux_for_Tegra\u002Fbootloader\u002F\u003CBPFDTB_FILE>` — per-clock `max-rate-custom` ceilings, plus the EMC DVFS gate (bwmgr + cactmon on all SoCs; osp-controller on T26x only).\n- **nvpower.sh** at `Linux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh` — cpufreq \u002F devfreq governors and (optionally) per-device min \u002F max \u002F static rates written to sysfs at boot.\n\nCommon triggers: \"lock CPU\u002FGPU\u002FEMC frequency\", \"pin GPU to Fmax\", \"pin EMC to MAXN\", \"disable\u002Fenable EMC DVFS\", \"disable\u002Fenable CPU DVFS\", \"set CPU\u002FGPU max rate\", \"change cpufreq governor\".\n\nOut of scope: runtime clock tuning on a live target (no flash step), nvpmodel power-mode edits (use the sibling skill `\u002Fjetson-customize-nvpmodel`), and silicon-ceiling overrides (`max-rate-maxn` is read-only).\n\n## Prerequisites\n\nResolve the active profile per\n[`..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md`](..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md).\nRefuse and route in these cases:\n\n| Condition | Refuse with |\n|---|---|\n| No active profile, or `active: NA` | Route to `\u002Fjetson-set-target` or `\u002Fjetson-init-target`. |\n| Profile lacks `bsp_image:` block | Route to `\u002Fjetson-init-image`. |\n| `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F` missing | Route to `\u002Fjetson-init-image`. |\n| `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` missing or not a git repo | Route to `\u002Fjetson-init-source`. |\n\nResolve paths:\n\n- `\u003Cbsp_image.root_path>` from `bsp_image.root_path:` if present, else `\u003Cworkspace>\u002FImage`.\n- `\u003Csource.root_path>` from `source.root_path:` if present, else `\u003Cworkspace>\u002FSource`.\n\n`\u003Cbsp_image.root_path>` is **read-only** for this skill; every write\n(Operation 1's BPMP DTB and Operation 2's `nvpower.sh`) lands under\n`\u003Csource.root_path>` (the overlay tracker). This is the workflow\ninvariant in\n[`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants`](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants) —\nhand-editing upstream silently destroys the diff trail and makes\n`\u002Fjetson-promote-image` a noop.\n\n## Instructions\n\n1. Resolve the prerequisites above (active profile, BSP image extracted, source overlay tracker initialized).\n2. Pick the operation from the table below.\n3. Follow the linked procedure section — Operation 1 (BPMP DTB), Operation 2 (`nvpower.sh`), or the MAXN recipe for both.\n4. Commit the edit inside the overlay tracker per each Operation's commit convention.\n5. Deploy with `\u002Fjetson-promote-image` → `\u002Fjetson-flash-image`. The new BPMP DTB and `nvpower.sh` take effect on the next boot.\n\n### Supported operations\n\n| Operation | Where the edit lives | Procedure section |\n|---|---|---|\n| Lock a CPU \u002F GPU clock to a specific rate | BPMP DTB `max-rate-custom` on the clock node + `nvpower.sh` governor `performance` | \"Content edit: `max-rate-custom`\" + \"Pick the edit\" |\n| Lock EMC at its init rate (disable EMC DVFS) | BPMP DTB: `bwmgr.enabled = 0`, `cactmon.enabled = 0`, plus `\u002Fdelete-node\u002F osp-controller` on T26x only | \"Content edit: EMC DVFS disable \u002F enable\" |\n| Re-enable EMC DVFS | BPMP DTB: `bwmgr.enabled = 1`, `cactmon.enabled = 1`, restore `osp-controller` on T26x | \"Content edit: EMC DVFS disable \u002F enable\" |\n| Pin everything to MAXN for stress runs | Combine the above + nvpmodel MAXN as boot default | see Recipe |\n| Lower a clock's hard ceiling without locking | BPMP DTB `max-rate-custom` only | \"Content edit: `max-rate-custom`\" |\n| Bound a device's rate without pinning | `nvpower.sh` min\u002Fmax via sysfs | \"Pick the edit\" |\n\n## Operation 1 — BPMP DTB edits\n\nFollow the BPMP-DTB customization protocol in\n[`..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md).\nThe protocol owns the mechanics — pristine import on first touch,\n`dtc` decompile, recompile, sanity-check, commit. This skill\nsupplies only the **clock-specific content** (which nodes and\nproperties to edit during the protocol's \"Edit the DTS\" step).\n\nThe edited `.dtb` lands in the `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F`\noverlay tracker. `\u002Fjetson-promote-image`'s channel A walks the\ntracker and copies the file into `bsp_image`. **Do not edit\n`\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F\u003Cbpmp-dtb>`\ndirectly** — that's the promote output, not an input.\n\n### Resolve the SKU-correct BPMP DTB\n\nPer the protocol's \"Resolving the active BPMP DTB\" section, read\n`BPFDTB_FILE` from the active flash conf. For the common Thor \u002F\nsingle-SKU conf shapes this is the static `BPFDTB_FILE=...` line\nin the per-board `.conf` and the value is authoritative as-is.\n\nFor **SKU-multiplexed conf shapes** (Orin AGX devkit conf chain\nthat selects a different BPMP DTB per `board_sku`\u002F`board_FAB`\nvia `update_flash_args_common` — see\n[`..\u002F..\u002Fcontext\u002Fbsp-customization-software-layers.md#per-board-conf-dispatch--update_flash_args_common`](..\u002F..\u002Fcontext\u002Fbsp-customization-software-layers.md#per-board-conf-dispatch--update_flash_args_common)),\nwalk the dispatch chain with `board_sku=\u003Cmodule.sku>` and\n`board_FAB=\u003Cmodule.revision or empty>` from the active profile,\nand read `BPFDTB_FILE` from the dispatch output — **not** from\nthe static line of the per-board `.conf`. Static and dispatched\nvalues match for non-multiplexed confs; the dispatch is\nmandatory only when the conf chain conditionally overrides\n`BPFDTB_FILE`.\n\n### List effective max rates (inspection)\n\nInspect both layers of the runtime ceiling — see [`references\u002Fclock-control-model.md#effective-runtime-ceiling`](references\u002Fclock-control-model.md#effective-runtime-ceiling) — before deciding on a `max-rate-custom` value.\n\nInspection cookbook (BPMP-side decompile + grep; nvpmodel-side awk over the boot default mode) is in [`references\u002Fbpmp-dtb-clock-edits.md#inspection-cookbook`](references\u002Fbpmp-dtb-clock-edits.md#inspection-cookbook).\n\nFor the nvpmodel layer see [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md).\n\nThis step does not mutate state — it's a precondition for sizing\nthe edit in the \"Content edit: `max-rate-custom` on a named clock node\" step.\n\n### Content edit: `max-rate-custom` on a named clock node\n\nDuring the \"Edit the DTS\" step of the protocol, modify the property\ninside the named clock node — never `lateinit`. `max-rate-custom`\nmust be strictly below the clock's hard cap (`max-rate-maxn` if\ndefined, otherwise the live `max_rate` from a running target of\nthe same chip \u002F SKU).\n\nDTS edit form, semantics, and the nvpmodel ↔ BPMP clock-node\nmapping live in [`references\u002Fbpmp-dtb-clock-edits.md`](references\u002Fbpmp-dtb-clock-edits.md).\n\nThen hand control back to the protocol — its \"Recompile\", \"Sanity-check\nthe recompiled blob\", \"Stage in the overlay tracker\", and \"Cleanup\"\nsteps cover the rest.\nCommit-message convention per the protocol:\n`\u003CBPMP_BASENAME>: jetson-customize-clocks — \u003Cclock-node> max-rate-custom = \u003Cvalue>`.\n\n### Content edit: EMC DVFS disable \u002F enable\n\nDefault behavior (EMC DVFS on) requires no edit. Disabling EMC\nDVFS is a **multi-node edit** applied inside the same \"Edit the DTS\" step of\nthe protocol, **not** a `bwmgr` toggle:\n\n| # | Edit | Scope |\n|---|---|---|\n| 1 | `bwmgr.enabled = \u003C0x00>` | All SoCs, mandatory |\n| 2 | `cactmon.enabled = \u003C0x00>` | All SoCs, mandatory |\n| 3 | `\u002Fdelete-node\u002F osp-controller` | **T26x (Thor) mandatory** — T23x (Orin) has no such node, skip |\n\nDetection: `dtc -I dtb -O dts \u003Cbpmp-dtb> | grep -c osp-controller`\n— zero hits ⇒ T23x path. Full DTS snippets, the surviving-paths\nfailure modes, and the re-enable procedure are in\n[`references\u002Femc-dvfs-disable.md`](references\u002Femc-dvfs-disable.md).\n\nApply the protocol's \"Recompile\" through \"Cleanup\" steps once the multi-node edit is in\nplace. Commit-message convention:\n`\u003CBPMP_BASENAME>: jetson-customize-clocks — EMC DVFS disable (bwmgr + cactmon[+ osp-controller])`.\n\nDisabling raises idle power; intended for stress \u002F performance\ntests, not production rootfs.\n\n### Re-run + idempotency\n\nPer the protocol's \"Re-runnability\" section, re-running this\nskill with the same target value produces a no-op commit. Re-\nrunning with a different value rewrites the same property — `git\nlog -- $BPMP_REL` shows the per-run history. To return a clock\nto its `max-rate-maxn` ceiling, edit the DTS to remove the\n`max-rate-custom` line and recompile.\n\n## Operation 2 — nvpower.sh edits\n\nEdits `nvpower.sh`, which runs at boot via `nvpower.service` to set\ncpufreq \u002F devfreq governors and rates.\n\n### The per-script file\n\nThe script this Operation edits has the relative path:\n\n```\nLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh\n```\n\nIt lives in **two** roots; the Operation walks both:\n\n| Role | Location | Skill writes? |\n|---|---|---|\n| Detection + pristine source | `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002F` | no — read-only |\n| Overlay edit target + git commit | `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002F` | yes |\n\nSubsequent sub-steps refer to **the per-script file** to mean the overlay\ncopy under `\u003Csource.root_path>`. The `\u003Cbsp_image.root_path>` copy is read\nonce during the pristine-import step below, then never touched again.\n\n### Overlay edit recipe (apply before editing nvpower.sh)\n\nFollow the canonical\n[Off-skill edits recipe](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#off-skill-edits)\nin the workflow doc — pristine import + customization commit pair, both\ngated by the preview gate. `nvpower.sh` is a single file with no\npropagation set; one pristine commit + one customization commit covers\nthe entire change.\n\nConcrete substitutions for this skill:\n\n- `\u003Crel>\u002F\u003Cfile>` is `rootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`.\n- Suggested pristine-import message:\n  `import pristine: rootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`,\n  body `Source: \u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F (BSP \u003Cbsp_image.version>)`.\n- Suggested customization-commit header:\n  `jetson-customize-clocks: nvpower.sh \u003Csummary>`,\n  body lines like `set_cpufreq_governor: desired_cpufreq_gov \"schedutil\" -> \"performance\"`.\n\n### Pick the edit\n\nFunction locations (`set_cpufreq_governor`, `set_devfreq_governor`), common-edit recipes (pin to Fmax, static rate, min\u002Fmax bounds), and the `nvidia-l4t-init` package-upgrade caveat live in [`references\u002Fnvpower-sh-edits.md`](references\u002Fnvpower-sh-edits.md).\n\n### Deploy\n\nThe customization commit in the overlay tracker does not reach the device\non its own. The Deploy chain:\n\n1. **`\u002Fjetson-promote-image`** — copies every tracked file in the overlay\n   into `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F`. Diff-aware (skip\n   byte-identical); uses `sudo cp -p` for `rootfs\u002F*` destinations.\n2. **`\u002Fjetson-flash-image`** — flashes the updated `bsp_image` to the\n   device. `nvpower.service` runs the new script on the next boot.\n3. (Alternate, no flash) Copy `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Frootfs\u002Fetc\u002Fsystemd\u002Fnvpower.sh`\n   directly to the running target's `\u002Fetc\u002Fsystemd\u002Fnvpower.sh`, then\n   `sudo systemctl restart nvpower.service` (or reboot).\n\nEditing `\u003Csource.root_path>\u002F...` without committing — or editing\n`\u003Cbsp_image.root_path>\u002F...` directly — does nothing for `\u002Fjetson-promote-image`\nand is silently lost on the next `\u002Fjetson-init-image` re-extract.\n\n## Recipe — pin everything to MAXN for stress \u002F performance runs\n\nCombines Operations 1 + 2. Operation 1's BPMP edits all flow\nthrough one round of the protocol (a single decompile \u002F multi-node\nedit \u002F recompile \u002F commit cycle — don't round-trip the protocol\ntwice for the same `.dtb`):\n\n1. **BPMP DTB** (the \"Content edit: `max-rate-custom` on a named clock node\" step content): leave `max-rate-custom` unset on every CPU \u002F GPU \u002F EMC clock; remove existing `max-rate-custom` lines that lower the ceiling.\n2. **BPMP DTB** (the \"Content edit: EMC DVFS disable \u002F enable\" step content): pin EMC at its init rate — `bwmgr.enabled = 0`, `cactmon.enabled = 0`, plus `\u002Fdelete-node\u002F osp-controller` on T26x (skip on T23x).\n3. Apply both content edits inside one protocol \"Edit the DTS\" invocation, then run the remaining protocol steps (recompile, sanity-check, single customization commit covering both content edits).\n4. **nvpower.sh** (Operation 2): set `desired_cpufreq_gov=\"performance\"` and `desired_devfreq_gov=\"performance\"` unconditionally; remove the GPU\u002Fnvjpg skip in `set_devfreq_governor`. Applies via Operation 2's overlay edit recipe (the \"Overlay edit recipe (apply before editing nvpower.sh)\" step) — a separate overlay-tracker pristine + customization commit pair on the rootfs script, distinct from the BPMP-DTB protocol's commit.\n5. Set the boot-default nvpmodel mode to MAXN via [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md) — the per-clock nvpmodel cap clamps below `max-rate-maxn` regardless of BPMP DTB content.\n\nDeploy [`\u002Fjetson-promote-image`](..\u002Fjetson-promote-image\u002FSKILL.md) → [`\u002Fjetson-flash-image`](..\u002Fjetson-flash-image\u002FSKILL.md) picks up the new BPMP DTB (via the overlay tracker) and the edited `nvpower.sh` (via the same overlay tracker) on the next flash.\n\n## Limitations\n\n- **Image-build-time only.** All edits land under `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` and reach the device only via `\u002Fjetson-promote-image` → `\u002Fjetson-flash-image`. Live-target tuning is out of scope.\n- **`max-rate-custom` only lowers the ceiling.** It must be strictly below `max-rate-maxn`; raising the silicon cap is not supported.\n- **Effective ceiling is two-layer.** The runtime ceiling is `min(BPMP cap, active-nvpmodel-mode cap)`. The nvpmodel cap is owned by `\u002Fjetson-customize-nvpmodel`; this skill does not edit it.\n- **SoC-conditional EMC DVFS gate.** Disabling EMC DVFS requires editing different node sets on T23x (bwmgr + cactmon) vs T26x (bwmgr + cactmon + delete `osp-controller`). Mis-detection produces undefined behavior.\n- **T23x GPU cap is multi-node.** The GPU clock is split across `nafll_gpusys` and every `nafll_gpcX`; the cap binds only when applied to all of them.\n- **`nvpower.sh` is package-managed.** It ships in `nvidia-l4t-init`; package upgrades clobber in-place edits. Long-lived setups should prefer a systemd drop-in or sibling helper.\n- **ODMDATA wins.** When an ODMDATA token covers a property, the token overrides direct BPMP DTS edits at flash time. Direct BPMP DTS edits are the fallback for properties no NVIDIA token reaches.\n- **`max-rate-maxn` and `lateinit` are off-limits.** `max-rate-maxn` is the silicon ceiling (read-only). `lateinit` is for boot-time clock init, not ceiling overrides — never touch either.\n- **BPMP DTB may be SKU-multiplexed.** On compound \u002F dispatched flash confs (Orin AGX devkit chain), `BPFDTB_FILE` is selected by `board_sku` \u002F `board_FAB` via `update_flash_args_common`. Reading the static `BPFDTB_FILE=` line is wrong when the chain conditionally overrides it; resolve via the dispatch instead.\n\n## Troubleshooting\n\n| Error | Cause | Solution |\n|---|---|---|\n| `max-rate-custom` set but clock still ramps to `max-rate-maxn` on T23x GPU | Only `nafll_gpusys` was capped; the `nafll_gpcX` partitions still run at `max-rate-maxn` and dominate the effective ceiling. | Apply the same `max-rate-custom` to `nafll_gpusys` **and** every `nafll_gpcX` node enumerated by `grep -nE '^\\s*nafll_gpc[0-9]+\\s*:' \u003Cdecompiled.dts>`. |\n| EMC DVFS disable appears to apply but EMC still scales on T26x | Only `bwmgr.enabled = \u003C0x00>` was set; `osp-controller` survives and re-issues frequency changes via the QoS path. | Add edits #2 (`cactmon.enabled = \u003C0x00>`) and #3 (`\u002Fdelete-node\u002F osp-controller`) inside the same \"Edit the DTS\" step. Verify `osp-controller` via `dtc -I dtb -O dts \u003Cbpmp-dtb> \\| grep -c osp-controller` → expect 0. |\n| EMC DVFS disable rejected on T23x with \"node not found\" for `osp-controller` | T23x (Orin) BPMP DTBs do not contain `osp-controller`; edit #3 must be skipped on T23x. | Detect SoC family with the `grep -c osp-controller` step; only apply #3 when the count is ≥1. |\n| BPMP refuses to load DTB after edit: `max-rate-custom >= max-rate-maxn` | `max-rate-custom` was set to or above the silicon ceiling. | Lower `max-rate-custom` strictly below `max-rate-maxn`. If `max-rate-maxn` is absent from the node, query the live cap on a running target: `cat \u002Fsys\u002Fkernel\u002Fdebug\u002Fbpmp\u002Fdebug\u002Fclk\u002F\u003Cclock>\u002Fmax_rate`. |\n| `osp-controller` re-appears after `status = \"disabled\"` | `status = \"disabled\"` does not remove the node from the device tree; BPMP still walks it. | Replace with `\u002Fdelete-node\u002F osp-controller;` — the node must not exist for BPMP to skip the path. |\n| Edits to `nvpower.sh` lost after `apt upgrade` | `nvpower.sh` is owned by the `nvidia-l4t-init` deb and gets overwritten on upgrade. | For long-lived test setups, package edits into a systemd drop-in or a sibling helper file referenced by `nvpower.sh`, rather than editing `nvpower.sh` in place. |\n| `\u002Fjetson-promote-image` is a no-op after editing the BPMP DTB | The edit was applied to `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002F`, which is `\u002Fjetson-promote-image`'s output — not its input. | Move the edit to `\u003Csource.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002F\u003CBPFDTB_FILE>` (the overlay tracker) and commit through the BPMP-DTB protocol. |\n| Cap appears to apply on first boot then resets after a power-mode change | The active nvpmodel mode's per-clock cap clamps below `max-rate-custom`. | Inspect both layers; if nvpmodel is binding, raise (or remove) the nvpmodel cap via `\u002Fjetson-customize-nvpmodel`. The BPMP cap alone is not the runtime ceiling. |\n\n## References\n\n- [`..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-bpmp-dtb.md) — canonical BPMP-DTB customization protocol (pristine import, decompile, edit, recompile, sanity-check, commit). Operation 1 of this skill is a content-only consumer; the protocol owns the mechanics.\n- [`references\u002Fclock-control-model.md`](references\u002Fclock-control-model.md) — layer stack, two-ceilings overview, effective-runtime-ceiling formula.\n- [`references\u002Fbpmp-dtb-clock-edits.md`](references\u002Fbpmp-dtb-clock-edits.md) — two-ceilings semantics, DTS edit form, nvpmodel ↔ BPMP clock-node mapping, inspection cookbook.\n- [`references\u002Femc-dvfs-disable.md`](references\u002Femc-dvfs-disable.md) — full SoC-conditional EMC DVFS disable procedure with DTS snippets, detection, re-enable.\n- [`references\u002Fnvpower-sh-edits.md`](references\u002Fnvpower-sh-edits.md) — `nvpower.sh` function locations + common-edit recipes + package-upgrade caveat.\n- [`\u002Fjetson-customize-nvpmodel`](..\u002Fjetson-customize-nvpmodel\u002FSKILL.md) — sibling skill: nvpmodel power modes. The active mode's per-clock cap clamps below the BPMP DTB cap.\n",{"name":5,"license":15,"version":24,"metadata":25,"description":7},"0.0.1",{"tags":26,"author":37,"domain":27,"data-classification":38},[27,28,29,30,31,32,33,34,35,36],"clocks","cpu","gpu","emc","dvfs","bwmgr","bpmp","nvpower","cpufreq","devfreq","Jetson Team","public","main","1c523aba5cdf867a79f078847075492d7778092a","skills\u002Fnvidia\u002Fjetson-customize-clocks",1,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills","https:\u002F\u002Fskills.x402.wtf","https:\u002F\u002Fgithub.com\u002Fthemusebook","https:\u002F\u002Fmusebook.trade","The official Github of musebook","2026-11-02 23:42:26",{"source":8,"skillName":5,"commands":50,"prompt":60,"zipAvailable":61},[51,54,57],{"tool":52,"command":53},"npx","npx skills add themusebook\u002Fskills --skill jetson-customize-clocks",{"tool":55,"command":56},"bunx","bunx skills add themusebook\u002Fskills --skill jetson-customize-clocks",{"tool":58,"command":59},"pnpm","pnpm dlx skills add themusebook\u002Fskills --skill jetson-customize-clocks","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002FSKILL.md",true,[63,69,73,77,81,85,89,93],{"path":64,"resourceType":65,"resourceTypeDesc":66,"sizeBytes":67,"sourceHtmlUrl":68},"BENCHMARK.md","REFERENCE","参考文档",3713,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002FBENCHMARK.md",{"path":70,"resourceType":65,"resourceTypeDesc":66,"sizeBytes":71,"sourceHtmlUrl":72},"evals\u002Fevals.json",5626,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002Fevals\u002Fevals.json",{"path":74,"resourceType":65,"resourceTypeDesc":66,"sizeBytes":75,"sourceHtmlUrl":76},"references\u002Fbpmp-dtb-clock-edits.md",4305,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002Freferences\u002Fbpmp-dtb-clock-edits.md",{"path":78,"resourceType":65,"resourceTypeDesc":66,"sizeBytes":79,"sourceHtmlUrl":80},"references\u002Fclock-control-model.md",1290,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002Freferences\u002Fclock-control-model.md",{"path":82,"resourceType":65,"resourceTypeDesc":66,"sizeBytes":83,"sourceHtmlUrl":84},"references\u002Femc-dvfs-disable.md",3281,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002Freferences\u002Femc-dvfs-disable.md",{"path":86,"resourceType":65,"resourceTypeDesc":66,"sizeBytes":87,"sourceHtmlUrl":88},"references\u002Fnvpower-sh-edits.md",1908,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002Freferences\u002Fnvpower-sh-edits.md",{"path":90,"resourceType":65,"resourceTypeDesc":66,"sizeBytes":91,"sourceHtmlUrl":92},"skill-card.md",3800,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002Fskill-card.md",{"path":94,"resourceType":95,"resourceTypeDesc":96,"sizeBytes":97,"sourceHtmlUrl":98},"skill.oms.sig","OTHER","其他",5585,"https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fjetson-customize-clocks\u002Fskill.oms.sig",[100,109,116,123,130,137],{"skillNo":101,"name":102,"nameZh":6,"description":103,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":104,"licenseFileUrl":105,"sourceHtmlUrl":106,"categories":107,"keywords":108,"publishedAt":19},"01M7AB34SPKVSDRRG009PM1CZH","youtube-clipper","YouTube 视频智能剪辑工具。下载视频和字幕，AI 分析生成精细章节（几分钟级别）， 用户选择片段后自动剪辑、翻译字幕为中英双语、烧录字幕到视频，并生成总结文案。 使用场景：当用户需要剪辑 YouTube 视频、生成短视频片段、制作双语字幕版本时。 关键词：视频剪辑、YouTube、字幕翻译、双语字幕、视频下载、clip video","MIT","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fyoutube-clipper\u002FLICENSE","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fyoutube-clipper\u002FSKILL.md",[],[],{"skillNo":110,"name":111,"nameZh":6,"description":112,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":104,"licenseFileUrl":6,"sourceHtmlUrl":113,"categories":114,"keywords":115,"publishedAt":19},"01M7AB18BH6N7KR7939HRNWVMQ","viem-integration","Integrate EVM blockchains using viem. Use when user says \"read blockchain data\", \"send transaction\", \"interact with smart contract\", \"connect to Ethereum\", \"use viem\", \"use wagmi\", \"wallet integration\", \"viem setup\", or mentions blockchain\u002FEVM development with TypeScript.","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fviem-integration\u002FSKILL.md",[],[],{"skillNo":117,"name":118,"nameZh":6,"description":119,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":104,"licenseFileUrl":6,"sourceHtmlUrl":120,"categories":121,"keywords":122,"publishedAt":19},"01M7AB12GHGP48WCNXDQQ9222H","v4-security-foundations","Security-first Uniswap v4 hook development. Use when user mentions \"v4 hooks\", \"hook security\", \"PoolManager\", \"beforeSwap\", \"afterSwap\", or asks about V4 hook best practices, vulnerabilities, or audit requirements.","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fv4-security-foundations\u002FSKILL.md",[],[],{"skillNo":124,"name":125,"nameZh":6,"description":126,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":104,"licenseFileUrl":6,"sourceHtmlUrl":127,"categories":128,"keywords":129,"publishedAt":19},"01M7AB0XM3PSR7V3Q2ZRR0Q0FB","v4-sdk-integration","App-layer SDK guide for building swap and liquidity experiences directly with the Uniswap v4 SDK. Use when user asks about \"v4 sdk\", \"uniswap v4\", \"v4 swap\", \"v4 liquidity\", \"PoolManager\", \"V4Planner\", \"StateView\", \"PositionManager\", \"pool state\", \"v4 position\", \"uniswap sdk\", or when building swap\u002Fliquidity UX directly with SDKs rather than via the Trading API.","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fv4-sdk-integration\u002FSKILL.md",[],[],{"skillNo":131,"name":132,"nameZh":6,"description":133,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":104,"licenseFileUrl":6,"sourceHtmlUrl":134,"categories":135,"keywords":136,"publishedAt":19},"01M7AB0SGA93ASA588DJW4P9WT","v4-hook-generator","Generate Uniswap v4 hook contracts via OpenZeppelin MCP. Use when building custom swap logic, async swaps, hook-owned liquidity, custom curves, dynamic fees, MEV protection, limit orders, or oracle hooks.","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Fv4-hook-generator\u002FSKILL.md",[],[],{"skillNo":138,"name":139,"nameZh":6,"description":140,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":104,"licenseFileUrl":6,"sourceHtmlUrl":141,"categories":142,"keywords":143,"publishedAt":19},"01M7AAZYH75H4CS03WSW2EZ8DM","testing","For testing with Light Protocol programs and clients on localnet, devnet, and mainnet validation.","https:\u002F\u002Fgithub.com\u002Fthemusebook\u002Fskills\u002Fblob\u002Fmain\u002Fskills\u002Ftesting\u002FSKILL.md",[],[]]