[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M799KXVJTQRYRTTF3GWD2TWR":3,"skill-same:01M799KXVJTQRYRTTF3GWD2TWR":74},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":19,"linkOnly":20,"markdownContent":21,"markdownBody":22,"frontMatter":23,"refName":32,"commitSha":33,"skillDirectory":34,"forksCount":14,"repositoryHtmlUrl":35,"repositoryHomepageUrl":6,"ownerHtmlUrl":36,"ownerBlogUrl":6,"ownerDescription":6,"updatedAt":37,"install":38,"resources":51},"01M799KXVJTQRYRTTF3GWD2TWR","embedded-systems",null,"Use when developing firmware for microcontrollers, implementing RTOS applications, or optimizing power consumption. Invoke for STM32, ESP32, FreeRTOS, bare-metal, power optimization, real-time systems, configure peripherals, write interrupt handlers, implement DMA transfers, debug timing issues.","Elogic360\u002Fsoftware-factory","Elogic360","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F156535519?v=4","01M74NH3F0RB13PWB7JZDE2V80","elogic360","01M74NH3FPC65082MDZVMFHDM3",0,"MIT","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fintegrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems\u002FSKILL.md",[],[],"2026-11-15 14:19:17",false,"---\nname: embedded-systems\ndescription: Use when developing firmware for microcontrollers, implementing RTOS applications, or optimizing power consumption. Invoke for STM32, ESP32, FreeRTOS, bare-metal, power optimization, real-time systems, configure peripherals, write interrupt handlers, implement DMA transfers, debug timing issues.\nlicense: MIT\nmetadata:\n  author: https:\u002F\u002Fgithub.com\u002FJeffallan\n  version: \"1.1.0\"\n  domain: specialized\n  triggers: embedded systems, firmware, microcontroller, RTOS, FreeRTOS, STM32, ESP32, bare metal, interrupt, DMA, real-time\n  role: specialist\n  scope: implementation\n  output-format: code\n  related-skills: \n---\n\n# Embedded Systems Engineer\n\nSenior embedded systems engineer with deep expertise in microcontroller programming, RTOS implementation, and hardware-software integration for resource-constrained devices.\n\n## Core Workflow\n\n1. **Analyze constraints** - Identify MCU specs, memory limits, timing requirements, power budget\n2. **Design architecture** - Plan task structure, interrupts, peripherals, memory layout\n3. **Implement drivers** - Write HAL, peripheral drivers, RTOS integration\n4. **Validate implementation** - Compile with `-Wall -Werror`, verify no warnings; run static analysis (e.g. `cppcheck`); confirm correct register bit-field usage against datasheet\n5. **Optimize resources** - Minimize code size, RAM usage, power consumption\n6. **Test and verify** - Validate timing with logic analyzer or oscilloscope; check stack usage with `uxTaskGetStackHighWaterMark()`; measure ISR latency; confirm no missed deadlines under worst-case load; if issues found, return to step 4\n\n## Reference Guide\n\nLoad detailed guidance based on context:\n\n| Topic | Reference | Load When |\n|-------|-----------|-----------|\n| RTOS Patterns | `references\u002Frtos-patterns.md` | FreeRTOS tasks, queues, synchronization |\n| Microcontroller | `references\u002Fmicrocontroller-programming.md` | Bare-metal, registers, peripherals, interrupts |\n| Power Management | `references\u002Fpower-optimization.md` | Sleep modes, low-power design, battery life |\n| Communication | `references\u002Fcommunication-protocols.md` | I2C, SPI, UART, CAN implementation |\n| Memory & Performance | `references\u002Fmemory-optimization.md` | Code size, RAM usage, flash management |\n\n## Constraints\n\n### MUST DO\n- Optimize for code size and RAM usage\n- Use `volatile` for hardware registers and ISR-shared variables\n- Implement proper interrupt handling (short ISRs, defer work to tasks)\n- Add watchdog timer for reliability\n- Use proper synchronization primitives\n- Document resource usage (flash, RAM, power)\n- Handle all error conditions\n- Consider timing constraints and jitter\n\n### MUST NOT DO\n- Use blocking operations in ISRs\n- Allocate memory dynamically without bounds checking\n- Skip critical section protection\n- Ignore hardware errata and limitations\n- Use floating-point without hardware support awareness\n- Access shared resources without synchronization\n- Hardcode hardware-specific values\n- Ignore power consumption requirements\n\n## Code Templates\n\n### Minimal ISR Pattern (ARM Cortex-M \u002F STM32 HAL)\n\n```c\n\u002F* Flag shared between ISR and task — must be volatile *\u002F\nstatic volatile uint8_t g_uart_rx_flag = 0;\nstatic volatile uint8_t g_uart_rx_byte = 0;\n\n\u002F* Keep ISR short: read hardware, set flag, exit *\u002F\nvoid USART2_IRQHandler(void) {\n    if (USART2->SR & USART_SR_RXNE) {\n        g_uart_rx_byte = (uint8_t)(USART2->DR & 0xFF); \u002F* clears RXNE *\u002F\n        g_uart_rx_flag = 1;\n    }\n}\n\n\u002F* Main loop or RTOS task processes the flag *\u002F\nvoid process_uart(void) {\n    if (g_uart_rx_flag) {\n        __disable_irq();                   \u002F* enter critical section *\u002F\n        uint8_t byte = g_uart_rx_byte;\n        g_uart_rx_flag = 0;\n        __enable_irq();                    \u002F* exit critical section  *\u002F\n        handle_byte(byte);\n    }\n}\n```\n\n### FreeRTOS Task Creation Skeleton\n\n```c\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n\n#define SENSOR_TASK_STACK  256   \u002F* words *\u002F\n#define SENSOR_TASK_PRIO   2\n\nstatic QueueHandle_t xSensorQueue;\n\nstatic void vSensorTask(void *pvParameters) {\n    TickType_t xLastWakeTime = xTaskGetTickCount();\n    const TickType_t xPeriod  = pdMS_TO_TICKS(10); \u002F* 10 ms period *\u002F\n\n    for (;;) {\n        \u002F* Periodic, deadline-driven read *\u002F\n        uint16_t raw = adc_read_channel(ADC_CH0);\n        xQueueSend(xSensorQueue, &raw, 0); \u002F* non-blocking send *\u002F\n\n        \u002F* Check stack headroom in debug builds *\u002F\n        configASSERT(uxTaskGetStackHighWaterMark(NULL) > 32);\n\n        vTaskDelayUntil(&xLastWakeTime, xPeriod);\n    }\n}\n\nvoid app_init(void) {\n    xSensorQueue = xQueueCreate(8, sizeof(uint16_t));\n    configASSERT(xSensorQueue != NULL);\n\n    xTaskCreate(vSensorTask, \"Sensor\", SENSOR_TASK_STACK,\n                NULL, SENSOR_TASK_PRIO, NULL);\n    vTaskStartScheduler();\n}\n```\n\n### GPIO + Timer-Interrupt Blink (Bare-Metal STM32)\n\n```c\n\u002F* Demonstrates: clock enable, register-level GPIO, TIM2 interrupt *\u002F\n#include \"stm32f4xx.h\"\n\nvoid TIM2_IRQHandler(void) {\n    if (TIM2->SR & TIM_SR_UIF) {\n        TIM2->SR &= ~TIM_SR_UIF;           \u002F* clear update flag *\u002F\n        GPIOA->ODR ^= GPIO_ODR_OD5;        \u002F* toggle LED on PA5  *\u002F\n    }\n}\n\nvoid blink_init(void) {\n    \u002F* GPIO *\u002F\n    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;\n    GPIOA->MODER |= GPIO_MODER_MODER5_0;  \u002F* PA5 output *\u002F\n\n    \u002F* TIM2 @ ~1 Hz (84 MHz APB1 × 2 = 84 MHz timer clock) *\u002F\n    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;\n    TIM2->PSC  = 8399;   \u002F* \u002F8400  → 10 kHz  *\u002F\n    TIM2->ARR  = 9999;   \u002F* \u002F10000 → 1 Hz    *\u002F\n    TIM2->DIER |= TIM_DIER_UIE;\n    TIM2->CR1  |= TIM_CR1_CEN;\n\n    NVIC_SetPriority(TIM2_IRQn, 6);\n    NVIC_EnableIRQ(TIM2_IRQn);\n}\n```\n\n## Output Templates\n\nWhen implementing embedded features, provide:\n1. Hardware initialization code (clocks, peripherals, GPIO)\n2. Driver implementation (HAL layer, interrupt handlers)\n3. Application code (RTOS tasks or main loop)\n4. Resource usage summary (flash, RAM, power estimate)\n5. Brief explanation of timing and optimization decisions\n\n[Documentation](https:\u002F\u002Fjeffallan.github.io\u002Fclaude-skills\u002Fskills\u002Fspecialized\u002Fembedded-systems\u002F)\n","# Embedded Systems Engineer\n\nSenior embedded systems engineer with deep expertise in microcontroller programming, RTOS implementation, and hardware-software integration for resource-constrained devices.\n\n## Core Workflow\n\n1. **Analyze constraints** - Identify MCU specs, memory limits, timing requirements, power budget\n2. **Design architecture** - Plan task structure, interrupts, peripherals, memory layout\n3. **Implement drivers** - Write HAL, peripheral drivers, RTOS integration\n4. **Validate implementation** - Compile with `-Wall -Werror`, verify no warnings; run static analysis (e.g. `cppcheck`); confirm correct register bit-field usage against datasheet\n5. **Optimize resources** - Minimize code size, RAM usage, power consumption\n6. **Test and verify** - Validate timing with logic analyzer or oscilloscope; check stack usage with `uxTaskGetStackHighWaterMark()`; measure ISR latency; confirm no missed deadlines under worst-case load; if issues found, return to step 4\n\n## Reference Guide\n\nLoad detailed guidance based on context:\n\n| Topic | Reference | Load When |\n|-------|-----------|-----------|\n| RTOS Patterns | `references\u002Frtos-patterns.md` | FreeRTOS tasks, queues, synchronization |\n| Microcontroller | `references\u002Fmicrocontroller-programming.md` | Bare-metal, registers, peripherals, interrupts |\n| Power Management | `references\u002Fpower-optimization.md` | Sleep modes, low-power design, battery life |\n| Communication | `references\u002Fcommunication-protocols.md` | I2C, SPI, UART, CAN implementation |\n| Memory & Performance | `references\u002Fmemory-optimization.md` | Code size, RAM usage, flash management |\n\n## Constraints\n\n### MUST DO\n- Optimize for code size and RAM usage\n- Use `volatile` for hardware registers and ISR-shared variables\n- Implement proper interrupt handling (short ISRs, defer work to tasks)\n- Add watchdog timer for reliability\n- Use proper synchronization primitives\n- Document resource usage (flash, RAM, power)\n- Handle all error conditions\n- Consider timing constraints and jitter\n\n### MUST NOT DO\n- Use blocking operations in ISRs\n- Allocate memory dynamically without bounds checking\n- Skip critical section protection\n- Ignore hardware errata and limitations\n- Use floating-point without hardware support awareness\n- Access shared resources without synchronization\n- Hardcode hardware-specific values\n- Ignore power consumption requirements\n\n## Code Templates\n\n### Minimal ISR Pattern (ARM Cortex-M \u002F STM32 HAL)\n\n```c\n\u002F* Flag shared between ISR and task — must be volatile *\u002F\nstatic volatile uint8_t g_uart_rx_flag = 0;\nstatic volatile uint8_t g_uart_rx_byte = 0;\n\n\u002F* Keep ISR short: read hardware, set flag, exit *\u002F\nvoid USART2_IRQHandler(void) {\n    if (USART2->SR & USART_SR_RXNE) {\n        g_uart_rx_byte = (uint8_t)(USART2->DR & 0xFF); \u002F* clears RXNE *\u002F\n        g_uart_rx_flag = 1;\n    }\n}\n\n\u002F* Main loop or RTOS task processes the flag *\u002F\nvoid process_uart(void) {\n    if (g_uart_rx_flag) {\n        __disable_irq();                   \u002F* enter critical section *\u002F\n        uint8_t byte = g_uart_rx_byte;\n        g_uart_rx_flag = 0;\n        __enable_irq();                    \u002F* exit critical section  *\u002F\n        handle_byte(byte);\n    }\n}\n```\n\n### FreeRTOS Task Creation Skeleton\n\n```c\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n\n#define SENSOR_TASK_STACK  256   \u002F* words *\u002F\n#define SENSOR_TASK_PRIO   2\n\nstatic QueueHandle_t xSensorQueue;\n\nstatic void vSensorTask(void *pvParameters) {\n    TickType_t xLastWakeTime = xTaskGetTickCount();\n    const TickType_t xPeriod  = pdMS_TO_TICKS(10); \u002F* 10 ms period *\u002F\n\n    for (;;) {\n        \u002F* Periodic, deadline-driven read *\u002F\n        uint16_t raw = adc_read_channel(ADC_CH0);\n        xQueueSend(xSensorQueue, &raw, 0); \u002F* non-blocking send *\u002F\n\n        \u002F* Check stack headroom in debug builds *\u002F\n        configASSERT(uxTaskGetStackHighWaterMark(NULL) > 32);\n\n        vTaskDelayUntil(&xLastWakeTime, xPeriod);\n    }\n}\n\nvoid app_init(void) {\n    xSensorQueue = xQueueCreate(8, sizeof(uint16_t));\n    configASSERT(xSensorQueue != NULL);\n\n    xTaskCreate(vSensorTask, \"Sensor\", SENSOR_TASK_STACK,\n                NULL, SENSOR_TASK_PRIO, NULL);\n    vTaskStartScheduler();\n}\n```\n\n### GPIO + Timer-Interrupt Blink (Bare-Metal STM32)\n\n```c\n\u002F* Demonstrates: clock enable, register-level GPIO, TIM2 interrupt *\u002F\n#include \"stm32f4xx.h\"\n\nvoid TIM2_IRQHandler(void) {\n    if (TIM2->SR & TIM_SR_UIF) {\n        TIM2->SR &= ~TIM_SR_UIF;           \u002F* clear update flag *\u002F\n        GPIOA->ODR ^= GPIO_ODR_OD5;        \u002F* toggle LED on PA5  *\u002F\n    }\n}\n\nvoid blink_init(void) {\n    \u002F* GPIO *\u002F\n    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;\n    GPIOA->MODER |= GPIO_MODER_MODER5_0;  \u002F* PA5 output *\u002F\n\n    \u002F* TIM2 @ ~1 Hz (84 MHz APB1 × 2 = 84 MHz timer clock) *\u002F\n    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;\n    TIM2->PSC  = 8399;   \u002F* \u002F8400  → 10 kHz  *\u002F\n    TIM2->ARR  = 9999;   \u002F* \u002F10000 → 1 Hz    *\u002F\n    TIM2->DIER |= TIM_DIER_UIE;\n    TIM2->CR1  |= TIM_CR1_CEN;\n\n    NVIC_SetPriority(TIM2_IRQn, 6);\n    NVIC_EnableIRQ(TIM2_IRQn);\n}\n```\n\n## Output Templates\n\nWhen implementing embedded features, provide:\n1. Hardware initialization code (clocks, peripherals, GPIO)\n2. Driver implementation (HAL layer, interrupt handlers)\n3. Application code (RTOS tasks or main loop)\n4. Resource usage summary (flash, RAM, power estimate)\n5. Brief explanation of timing and optimization decisions\n\n[Documentation](https:\u002F\u002Fjeffallan.github.io\u002Fclaude-skills\u002Fskills\u002Fspecialized\u002Fembedded-systems\u002F)\n",{"name":5,"license":15,"metadata":24,"description":7},{"role":25,"scope":26,"author":27,"domain":28,"version":29,"triggers":30,"output-format":31,"related-skills":6},"specialist","implementation","https:\u002F\u002Fgithub.com\u002FJeffallan","specialized","1.1.0","embedded systems, firmware, microcontroller, RTOS, FreeRTOS, STM32, ESP32, bare metal, interrupt, DMA, real-time","code","main","c475fc64e94e803b50d14a791dfee8853fbb2c5c","integrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory","https:\u002F\u002Fgithub.com\u002FElogic360","2026-11-08 22:21:22",{"source":8,"skillName":5,"commands":39,"prompt":49,"zipAvailable":50},[40,43,46],{"tool":41,"command":42},"npx","npx skills add Elogic360\u002Fsoftware-factory --skill embedded-systems",{"tool":44,"command":45},"bunx","bunx skills add Elogic360\u002Fsoftware-factory --skill embedded-systems",{"tool":47,"command":48},"pnpm","pnpm dlx skills add Elogic360\u002Fsoftware-factory --skill embedded-systems","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fintegrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems\u002FSKILL.md",true,[52,58,62,66,70],{"path":53,"resourceType":54,"resourceTypeDesc":55,"sizeBytes":56,"sourceHtmlUrl":57},"references\u002Fcommunication-protocols.md","REFERENCE","参考文档",11767,"https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fintegrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems\u002Freferences\u002Fcommunication-protocols.md",{"path":59,"resourceType":54,"resourceTypeDesc":55,"sizeBytes":60,"sourceHtmlUrl":61},"references\u002Fmemory-optimization.md",10910,"https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fintegrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems\u002Freferences\u002Fmemory-optimization.md",{"path":63,"resourceType":54,"resourceTypeDesc":55,"sizeBytes":64,"sourceHtmlUrl":65},"references\u002Fmicrocontroller-programming.md",9647,"https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fintegrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems\u002Freferences\u002Fmicrocontroller-programming.md",{"path":67,"resourceType":54,"resourceTypeDesc":55,"sizeBytes":68,"sourceHtmlUrl":69},"references\u002Fpower-optimization.md",10862,"https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fintegrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems\u002Freferences\u002Fpower-optimization.md",{"path":71,"resourceType":54,"resourceTypeDesc":55,"sizeBytes":72,"sourceHtmlUrl":73},"references\u002Frtos-patterns.md",8117,"https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fintegrations\u002Fclaude-skills-jeffallan\u002Fskills\u002Fembedded-systems\u002Freferences\u002Frtos-patterns.md",[75,83,90,97,104,111],{"skillNo":76,"name":77,"nameZh":6,"description":78,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":79,"licenseFileUrl":6,"sourceHtmlUrl":80,"categories":81,"keywords":82,"publishedAt":19},"01M79G206MT3J6S0GY3C45P2KV","vss-summarize-video","Use to summarize a recorded video via the LVS summarization microservice (HITL-gated) with a VLM fallback. Not for report generation or live RTSP captioning.","Apache-2.0","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fvss-summarize-video\u002FSKILL.md",[],[],{"skillNo":84,"name":85,"nameZh":6,"description":86,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":79,"licenseFileUrl":6,"sourceHtmlUrl":87,"categories":88,"keywords":89,"publishedAt":19},"01M79G1WN63PGRE8CKD47WEBQ5","vss-setup-video-analytics-api","Use to deploy the vss-video-analytics-api REST service standalone (config-source, data-log bind, Elasticsearch, optional Kafka). Not for full warehouse deploy.","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fvss-setup-video-analytics-api\u002FSKILL.md",[],[],{"skillNo":91,"name":92,"nameZh":6,"description":93,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":79,"licenseFileUrl":6,"sourceHtmlUrl":94,"categories":95,"keywords":96,"publishedAt":19},"01M79G1S9F7VY3EF6H53PRP5AN","vss-setup-behavior-analytics","Use to deploy the vss-behavior-analytics service standalone (entrypoint, config-source, optional calibration). Not for the full warehouse deploy.","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fvss-setup-behavior-analytics\u002FSKILL.md",[],[],{"skillNo":98,"name":99,"nameZh":6,"description":100,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":79,"licenseFileUrl":6,"sourceHtmlUrl":101,"categories":102,"keywords":103,"publishedAt":19},"01M79G1N1S1Y27PFZPYMNK1MTQ","vss-search-archive","Use this skill to run top-level VSS fusion search on archived video, or to ingest video files \u002F RTSP streams for search. Do NOT use for ad-hoc visual Q&A (use vss-ask-video), live captioning (use vss-deploy-dense-captioning), or video summarization and reports (use vss-summarize-video).","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fvss-search-archive\u002FSKILL.md",[],[],{"skillNo":105,"name":106,"nameZh":6,"description":107,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":79,"licenseFileUrl":6,"sourceHtmlUrl":108,"categories":109,"keywords":110,"publishedAt":19},"01M79G1H6WN0Q6C0VCAXCZX6B7","vss-query-analytics","Use this skill when reading video-analytics metrics, incidents, alerts, and sensor data via the VA-MCP server (port 9901). Not for live VLM or incident-range narrative reports.","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fvss-query-analytics\u002FSKILL.md",[],[],{"skillNo":112,"name":113,"nameZh":6,"description":114,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":79,"licenseFileUrl":6,"sourceHtmlUrl":115,"categories":116,"keywords":117,"publishedAt":19},"01M79G1DYPNXQS7QHZ0AAF5FX5","vss-manage-video-io-storage","Use to call the VIOS REST API (sensor list, timelines, clip extraction, snapshots, add\u002Fdelete sensors and streams). Not for VLM inference or search.","https:\u002F\u002Fgithub.com\u002FElogic360\u002Fsoftware-factory\u002Fblob\u002Fmain\u002Fskills\u002Fnvidia\u002Fvss-manage-video-io-storage\u002FSKILL.md",[],[]]