[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M78A623VFZX40ZAPAXKN78GD":3,"skill-same:01M78A623VFZX40ZAPAXKN78GD":88},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":19,"linkOnly":20,"markdownContent":21,"markdownBody":22,"frontMatter":23,"refName":34,"commitSha":35,"skillDirectory":36,"forksCount":14,"repositoryHtmlUrl":37,"repositoryHomepageUrl":6,"ownerHtmlUrl":38,"ownerBlogUrl":39,"ownerDescription":40,"updatedAt":41,"install":42,"resources":55},"01M78A623VFZX40ZAPAXKN78GD","jetson-customize-uphy",null,"Configure Jetson UPHY lane allocation (uphy0\u002Fuphy1-config) on Orin\u002FThor custom carriers. Do NOT use for pinmux or PCIe-only edits.","Solizardking\u002Ftrain2earn","Solizardking","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F108096810?v=4","01M786KDB10AYV042N0F9BD5B5","Clawd","01M786KDC5C3NPE4W44C5641EZ",0,"Apache-2.0","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002FSKILL.md",[],[],"2026-11-15 14:19:17",false,"---\nname: jetson-customize-uphy\ndescription: Configure Jetson UPHY lane allocation (uphy0\u002Fuphy1-config) on Orin\u002FThor custom carriers. Do NOT use for pinmux or PCIe-only edits.\nversion: 0.0.2\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - bsp\n    - phase-2\n    - io\n    - uphy\n  domain: meta\n---\n\n# Customize UPHY lane allocation\n\n## Purpose\n\nSelect a UPHY lane allocation on a Jetson custom carrier and edit the\ncarrier flash-conf fork's `ODMDATA=\"...\"` to apply the chosen\n`uphyX-config-N` token(s) (plus the `UPHY_CONFIG=\"\"` clear required for\n`uphy0-config-6`). Kernel-DT alignment per controller is **not** done\nhere — after the ODMDATA commit lands, this skill dispatches to the\nper-controller skills (`\u002Fjetson-customize-pcie`,\n`\u002Fjetson-customize-mgbe`, `\u002Fjetson-customize-usb`), each of which must\ncompare the chosen allocation against the **reference kernel DTB**\nnode-by-node and emit an overlay fragment only when the K-stock value\ndisagrees with the chosen allocation. Discovery is agentic: options,\nlanes, and controllers come from the Adaptation Guide, carrier\nschematic, and Module \u002F SoC TRM at run time — never hard-coded. Every\nuser-visible step renders its data as a markdown table, and the final\nsummary includes a changes-summary table.\n\n## Prerequisites\n\n- Active target-platform profile with `reference_devkit:` and\n  `custom_carrier:`.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` initialized\n  (`\u002Fjetson-init-source`).\n- Forked carrier conf present (`\u002Fjetson-derive-carrier`).\n- Reachable Adaptation Guide via `documents.adaptation_guide` ->\n  `documents.bsp_developer_guide` -> web fetch -> Step-1 prompt\n  fallback.\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** The skill\n  refuses to run if either is missing — routing decisions for the\n  custom carrier cannot be guessed. Reference-devkit-only profiles\n  (no `custom_carrier:` block) do not require these.\n\n## Overview\n\nUPHY (unified PHY) is the shared high-speed PHY pool on Tegra264 (Thor)\nand Tegra234 (Orin). Lane allocation is selected by `ODMDATA` tokens\n(`uphy0-config-N`, Thor also `uphy1-config-N`) parsed at flash time by\n`tegraflash_impl_t264.py::tegraflash_update_bpmp_dtb()` and written\ninto `\u002Fuphy\u002Fuphy{0,1}-config` of the BPMP DTB.\n\nOutput is a **single atomic ODMDATA commit** in\n`\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` carrying the chosen\n`uphyX-config-N` token(s), the `UPHY_CONFIG=\"\"` clear (for\n`uphy0-config-6`), AND every per-controller ODMDATA token derived\nfrom the chosen allocation (`pcie@N_status=*`, `mgbeN-speed-*`, USB SS\nper-port tokens). Sub-skills (`\u002Fjetson-customize-pcie`,\n`\u002Fjetson-customize-mgbe`, `\u002Fjetson-customize-usb`) own only the\nkernel-DT overlay fragments — they MUST NOT touch ODMDATA. All\ncommits follow the batched pristine + customization pattern in\n`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md`. Upstream BSP at\n`\u003Cbsp_image.root_path>\u002F` is never edited.\n\n## When to invoke\n\n- User says \"configure UPHY\", \"uphy lane allocation\",\n  \"set uphy0-config-N\", \"change MGBE speed\", or asks to remap\n  PCIe \u002F MGBE \u002F USB3 \u002F UFS on a custom carrier.\n- A UPHY-fed controller doesn't enumerate after flash, OR cold boot\n  dies in BL31 SError \u002F `BPMP firmware is not ready`.\n- A downstream skill reports FMON fault or BPMP-DTB lane mismatch.\n\n## Procedure (summary)\n\nEight steps; full detail in `references\u002Fprocedure.md`.\n\n1. **Resolve target + docs.** Refuse without active profile, custom\n   carrier, source-tree git, or forked carrier conf. Resolve Adaptation\n   Guide \u002F schematic \u002F Module Design Guide \u002F SoC TRM.\n2. **Locate \"Configure the UPHY Lane\"** in the Adaptation Guide (PDF \u002F\n   HTML mirror \u002F `WebFetch`). Cross-check Module Design Guide + SoC TRM.\n3. **Cross-reference the carrier schematic.** Cite UPHY net names\n   (`MGBE2_TX_P\u002FN`, `PEX5_LN0+-`, etc.). Zero matching nets = unrouted.\n4. **Enumerate matching UPHY options.** Surface every documented\n   `uphy0-config-N` (and Thor `uphy1-config-N`) index.\n5. **Ask the user which config (HARD GATE).** Print tables first, then\n   `AskUserQuestion` — one per UPHY surface, plus carrier-routing\n   confirmation if any allocated lane is unrouted. Persist answers to\n   the JSON sidecar (`references\u002Frun-state-sidecar.md`).\n6. **Edit carrier flash-conf fork (atomic ODMDATA commit).** This skill\n   owns every ODMDATA token for the run. One `ODMDATA=\"...\"` line, one\n   commit, all tokens. Sub-skills MUST NOT touch ODMDATA.\n\n   Decompile the BPMP DTB at\n   `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002Fgeneric\u002F\u003CBPFDTB_FILE>`\n   (`BPFDTB_FILE` from the carrier conf) to snapshot stock state, then\n   emit tokens in this order:\n\n   a. **UPHY surface tokens** — every chosen `uphyX-config-N` (Thor:\n      both surfaces, even if one equals the guide default). Order\n      `uphy0` then `uphy1`; separator `,`.\n   b. **Per-controller tokens** — one per row whose plan-state differs\n      from BPMP-stock. Match-rows get no token (redundant tokens can\n      drop the whole line).\n      - PCIe: `pcie@N_status=okay|disabled`.\n      - MGBE: `mgbeN-speed-\u003Crate>` on allocate, **`mgbeN-speed-del`**\n        on disable. FMON arms on the controller's own clocks\n        regardless of UPHY allocation — missing `del` ⇒ BL31 SError\n        reboot loop. Single most common post-flash failure on Thor.\n      - USB SS: per-port tokens when the SoC grammar exposes them.\n   c. **`UPHY_CONFIG=\"\"` clear** when `uphy0-config-6` is selected\n      (BCT pinmux clear per Adaptation Guide).\n7. **Build the per-controller allocation table and dispatch.** Derive\n   one row per UPHY-fed controller (PCIe \u002F MGBE \u002F USB SS \u002F UFS) with\n   `{class, instance, allocated?, BPMP-stock, K-stock, routed?,\n   Desired K state}`. This table drives both (a) Step 6's ODMDATA\n   tokens and (b) the sub-skills' overlay fragments — build it\n   before Step 6 commits.\n\n   Then invoke `\u002Fjetson-customize-pcie`, `\u002Fjetson-customize-mgbe`, and\n   `\u002Fjetson-customize-usb` for **kernel-DT overlay fragments only**\n   (no ODMDATA edits — Step 6 owns the line). Each sub-skill re-reads\n   K-stock from\n   `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Fkernel\u002Fdtb\u002Ftegra\u003Csoc>-*-nv.dtb`\n   and skips emission when K-stock matches Desired K state. UFS\n   handling stays inline here (no UFS sub-skill).\n\n   Invoke all three whenever their controller class is present on\n   this SoC (e.g. skip MGBE on Orin). Ask the operator first; on\n   `yes`, run the sub-skill inline.\n8. **Summary + next-step chain.** Headline, breakdown, **choices table**\n   (UPHY surface | chosen config | lane summary | UPHY_CONFIG-clear),\n   **changes-summary table** (file | repo | commit SHA | one-line\n   summary covering this skill's commit + every dispatched sub-skill's\n   commit), then drive the downstream chain (more I\u002FO? build & promote?\n   flash? validate?) via sequential `AskUserQuestion` prompts per\n   `references\u002Fprocedure.md` Step 8. Never substitute a printed\n   \"Next step: …\" line for the prompts.\n\n## Limitations\n\n- Only supports Tegra234 (Orin) and Tegra264 (Thor) UPHY surfaces.\n- Does not edit pinmux, PCIe-only DT properties absent from BPMP DTB\n  (`num-lanes`, `pcie-mode`), or upstream BSP files.\n- Does not flash, build, or promote — chain into `\u002Fjetson-build-source`\n  and downstream skills.\n- Hard-coded option tables are forbidden; if no Adaptation Guide\n  source resolves the skill refuses rather than guessing.\n- Not table-driven across releases: every run re-reads the Guide for\n  the active BSP version.\n\n## Troubleshooting\n\n- **Cold boot reboot loop \u002F BL31 `plat_setup.c:726` \u002F `BPMP firmware\n  is not ready`** after `uphy0-config-6`: a later\n  `^UPHY_CONFIG=` line in the carrier conf re-overrode the clear.\n  Comment it (see `references\u002Fprocedure.md` Step 6).\n- **`wait-for-device failed` at flash, BPMP DTB unchanged**: an\n  ODMDATA token had wrong shape (e.g. `mgbe0-speed-0`). One bad token\n  drops the whole `ODMDATA=\"...\"` line. Inspect grammar in\n  `references\u002Fprocedure.md`.\n- **BL31 SError reboot loop after disabling an MGBE**: missing\n  `mgbeN-speed-del`. FMON arms on the controller's own clocks\n  regardless of UPHY allocation.\n- **Newly-routed controller doesn't enumerate**: stock kernel DTB had\n  `status=\"disabled\"`. Overlay must emit `status=\"okay\"` (matrix\n  row 4 in `references\u002Fprocedure.md`).\n- **Pinmap delta=0 but board still misbehaves**: UPHY differential\n  pairs are absent from pinmux `.xlsm`. Drive decisions off schematic\n  net names, not the pinmap.\n- **Duplicate `pcie@\u003Caddr>` fragments**: another skill\n  (`jetson-customize-pcie`) already owns that node. Scope this skill\n  to MGBE \u002F UFS \u002F USB3 SS \u002F PCIe-status-only and cite the other\n  overlay.\n\n## References\n\n- `references\u002Fprocedure.md` — full eight-step procedure.\n- `references\u002Fgotchas.md` — cross-cutting gotchas.\n- `references\u002Frun-state-sidecar.md` — JSON sidecar schema + idempotency.\n- `..\u002F..\u002Freferences\u002Fplatform_template.yaml` — `documents:` schema.\n- `..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md` — overlay edit protocol.\n- `..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md` — composite-overlay\n  filename \u002F append protocol.\n- `..\u002Fjetson-derive-carrier\u002FSKILL.md` — produces the conf this skill\n  edits.\n- `..\u002Fjetson-init-source\u002FSKILL.md` — produces the two git repos this\n  skill commits into.\n- `..\u002Fjetson-generate-kb\u002FSKILL.md` — KB consulted for chip family +\n  file locations.\n","# Customize UPHY lane allocation\n\n## Purpose\n\nSelect a UPHY lane allocation on a Jetson custom carrier and edit the\ncarrier flash-conf fork's `ODMDATA=\"...\"` to apply the chosen\n`uphyX-config-N` token(s) (plus the `UPHY_CONFIG=\"\"` clear required for\n`uphy0-config-6`). Kernel-DT alignment per controller is **not** done\nhere — after the ODMDATA commit lands, this skill dispatches to the\nper-controller skills (`\u002Fjetson-customize-pcie`,\n`\u002Fjetson-customize-mgbe`, `\u002Fjetson-customize-usb`), each of which must\ncompare the chosen allocation against the **reference kernel DTB**\nnode-by-node and emit an overlay fragment only when the K-stock value\ndisagrees with the chosen allocation. Discovery is agentic: options,\nlanes, and controllers come from the Adaptation Guide, carrier\nschematic, and Module \u002F SoC TRM at run time — never hard-coded. Every\nuser-visible step renders its data as a markdown table, and the final\nsummary includes a changes-summary table.\n\n## Prerequisites\n\n- Active target-platform profile with `reference_devkit:` and\n  `custom_carrier:`.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` initialized\n  (`\u002Fjetson-init-source`).\n- Forked carrier conf present (`\u002Fjetson-derive-carrier`).\n- Reachable Adaptation Guide via `documents.adaptation_guide` ->\n  `documents.bsp_developer_guide` -> web fetch -> Step-1 prompt\n  fallback.\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** The skill\n  refuses to run if either is missing — routing decisions for the\n  custom carrier cannot be guessed. Reference-devkit-only profiles\n  (no `custom_carrier:` block) do not require these.\n\n## Overview\n\nUPHY (unified PHY) is the shared high-speed PHY pool on Tegra264 (Thor)\nand Tegra234 (Orin). Lane allocation is selected by `ODMDATA` tokens\n(`uphy0-config-N`, Thor also `uphy1-config-N`) parsed at flash time by\n`tegraflash_impl_t264.py::tegraflash_update_bpmp_dtb()` and written\ninto `\u002Fuphy\u002Fuphy{0,1}-config` of the BPMP DTB.\n\nOutput is a **single atomic ODMDATA commit** in\n`\u003Csource.root_path>\u002FLinux_for_Tegra\u002F` carrying the chosen\n`uphyX-config-N` token(s), the `UPHY_CONFIG=\"\"` clear (for\n`uphy0-config-6`), AND every per-controller ODMDATA token derived\nfrom the chosen allocation (`pcie@N_status=*`, `mgbeN-speed-*`, USB SS\nper-port tokens). Sub-skills (`\u002Fjetson-customize-pcie`,\n`\u002Fjetson-customize-mgbe`, `\u002Fjetson-customize-usb`) own only the\nkernel-DT overlay fragments — they MUST NOT touch ODMDATA. All\ncommits follow the batched pristine + customization pattern in\n`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md`. Upstream BSP at\n`\u003Cbsp_image.root_path>\u002F` is never edited.\n\n## When to invoke\n\n- User says \"configure UPHY\", \"uphy lane allocation\",\n  \"set uphy0-config-N\", \"change MGBE speed\", or asks to remap\n  PCIe \u002F MGBE \u002F USB3 \u002F UFS on a custom carrier.\n- A UPHY-fed controller doesn't enumerate after flash, OR cold boot\n  dies in BL31 SError \u002F `BPMP firmware is not ready`.\n- A downstream skill reports FMON fault or BPMP-DTB lane mismatch.\n\n## Procedure (summary)\n\nEight steps; full detail in `references\u002Fprocedure.md`.\n\n1. **Resolve target + docs.** Refuse without active profile, custom\n   carrier, source-tree git, or forked carrier conf. Resolve Adaptation\n   Guide \u002F schematic \u002F Module Design Guide \u002F SoC TRM.\n2. **Locate \"Configure the UPHY Lane\"** in the Adaptation Guide (PDF \u002F\n   HTML mirror \u002F `WebFetch`). Cross-check Module Design Guide + SoC TRM.\n3. **Cross-reference the carrier schematic.** Cite UPHY net names\n   (`MGBE2_TX_P\u002FN`, `PEX5_LN0+-`, etc.). Zero matching nets = unrouted.\n4. **Enumerate matching UPHY options.** Surface every documented\n   `uphy0-config-N` (and Thor `uphy1-config-N`) index.\n5. **Ask the user which config (HARD GATE).** Print tables first, then\n   `AskUserQuestion` — one per UPHY surface, plus carrier-routing\n   confirmation if any allocated lane is unrouted. Persist answers to\n   the JSON sidecar (`references\u002Frun-state-sidecar.md`).\n6. **Edit carrier flash-conf fork (atomic ODMDATA commit).** This skill\n   owns every ODMDATA token for the run. One `ODMDATA=\"...\"` line, one\n   commit, all tokens. Sub-skills MUST NOT touch ODMDATA.\n\n   Decompile the BPMP DTB at\n   `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Fbootloader\u002Fgeneric\u002F\u003CBPFDTB_FILE>`\n   (`BPFDTB_FILE` from the carrier conf) to snapshot stock state, then\n   emit tokens in this order:\n\n   a. **UPHY surface tokens** — every chosen `uphyX-config-N` (Thor:\n      both surfaces, even if one equals the guide default). Order\n      `uphy0` then `uphy1`; separator `,`.\n   b. **Per-controller tokens** — one per row whose plan-state differs\n      from BPMP-stock. Match-rows get no token (redundant tokens can\n      drop the whole line).\n      - PCIe: `pcie@N_status=okay|disabled`.\n      - MGBE: `mgbeN-speed-\u003Crate>` on allocate, **`mgbeN-speed-del`**\n        on disable. FMON arms on the controller's own clocks\n        regardless of UPHY allocation — missing `del` ⇒ BL31 SError\n        reboot loop. Single most common post-flash failure on Thor.\n      - USB SS: per-port tokens when the SoC grammar exposes them.\n   c. **`UPHY_CONFIG=\"\"` clear** when `uphy0-config-6` is selected\n      (BCT pinmux clear per Adaptation Guide).\n7. **Build the per-controller allocation table and dispatch.** Derive\n   one row per UPHY-fed controller (PCIe \u002F MGBE \u002F USB SS \u002F UFS) with\n   `{class, instance, allocated?, BPMP-stock, K-stock, routed?,\n   Desired K state}`. This table drives both (a) Step 6's ODMDATA\n   tokens and (b) the sub-skills' overlay fragments — build it\n   before Step 6 commits.\n\n   Then invoke `\u002Fjetson-customize-pcie`, `\u002Fjetson-customize-mgbe`, and\n   `\u002Fjetson-customize-usb` for **kernel-DT overlay fragments only**\n   (no ODMDATA edits — Step 6 owns the line). Each sub-skill re-reads\n   K-stock from\n   `\u003Cbsp_image.root_path>\u002FLinux_for_Tegra\u002Fkernel\u002Fdtb\u002Ftegra\u003Csoc>-*-nv.dtb`\n   and skips emission when K-stock matches Desired K state. UFS\n   handling stays inline here (no UFS sub-skill).\n\n   Invoke all three whenever their controller class is present on\n   this SoC (e.g. skip MGBE on Orin). Ask the operator first; on\n   `yes`, run the sub-skill inline.\n8. **Summary + next-step chain.** Headline, breakdown, **choices table**\n   (UPHY surface | chosen config | lane summary | UPHY_CONFIG-clear),\n   **changes-summary table** (file | repo | commit SHA | one-line\n   summary covering this skill's commit + every dispatched sub-skill's\n   commit), then drive the downstream chain (more I\u002FO? build & promote?\n   flash? validate?) via sequential `AskUserQuestion` prompts per\n   `references\u002Fprocedure.md` Step 8. Never substitute a printed\n   \"Next step: …\" line for the prompts.\n\n## Limitations\n\n- Only supports Tegra234 (Orin) and Tegra264 (Thor) UPHY surfaces.\n- Does not edit pinmux, PCIe-only DT properties absent from BPMP DTB\n  (`num-lanes`, `pcie-mode`), or upstream BSP files.\n- Does not flash, build, or promote — chain into `\u002Fjetson-build-source`\n  and downstream skills.\n- Hard-coded option tables are forbidden; if no Adaptation Guide\n  source resolves the skill refuses rather than guessing.\n- Not table-driven across releases: every run re-reads the Guide for\n  the active BSP version.\n\n## Troubleshooting\n\n- **Cold boot reboot loop \u002F BL31 `plat_setup.c:726` \u002F `BPMP firmware\n  is not ready`** after `uphy0-config-6`: a later\n  `^UPHY_CONFIG=` line in the carrier conf re-overrode the clear.\n  Comment it (see `references\u002Fprocedure.md` Step 6).\n- **`wait-for-device failed` at flash, BPMP DTB unchanged**: an\n  ODMDATA token had wrong shape (e.g. `mgbe0-speed-0`). One bad token\n  drops the whole `ODMDATA=\"...\"` line. Inspect grammar in\n  `references\u002Fprocedure.md`.\n- **BL31 SError reboot loop after disabling an MGBE**: missing\n  `mgbeN-speed-del`. FMON arms on the controller's own clocks\n  regardless of UPHY allocation.\n- **Newly-routed controller doesn't enumerate**: stock kernel DTB had\n  `status=\"disabled\"`. Overlay must emit `status=\"okay\"` (matrix\n  row 4 in `references\u002Fprocedure.md`).\n- **Pinmap delta=0 but board still misbehaves**: UPHY differential\n  pairs are absent from pinmux `.xlsm`. Drive decisions off schematic\n  net names, not the pinmap.\n- **Duplicate `pcie@\u003Caddr>` fragments**: another skill\n  (`jetson-customize-pcie`) already owns that node. Scope this skill\n  to MGBE \u002F UFS \u002F USB3 SS \u002F PCIe-status-only and cite the other\n  overlay.\n\n## References\n\n- `references\u002Fprocedure.md` — full eight-step procedure.\n- `references\u002Fgotchas.md` — cross-cutting gotchas.\n- `references\u002Frun-state-sidecar.md` — JSON sidecar schema + idempotency.\n- `..\u002F..\u002Freferences\u002Fplatform_template.yaml` — `documents:` schema.\n- `..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md` — overlay edit protocol.\n- `..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md` — composite-overlay\n  filename \u002F append protocol.\n- `..\u002Fjetson-derive-carrier\u002FSKILL.md` — produces the conf this skill\n  edits.\n- `..\u002Fjetson-init-source\u002FSKILL.md` — produces the two git repos this\n  skill commits into.\n- `..\u002Fjetson-generate-kb\u002FSKILL.md` — KB consulted for chip family +\n  file locations.\n",{"name":5,"license":15,"version":24,"metadata":25,"description":7},"0.0.2",{"tags":26,"author":31,"domain":32,"data-classification":33},[27,28,29,30],"bsp","phase-2","io","uphy","Jetson Team","meta","public","main","86cc27ffd16af6cb85948f1155578e6f3f61cc4c","skillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn","https:\u002F\u002Fgithub.com\u002FSolizardking","https:\u002F\u002Fmusebook.trade","Got a mile high and never came down","2026-10-08 11:52:53",{"source":8,"skillName":5,"commands":43,"prompt":53,"zipAvailable":54},[44,47,50],{"tool":45,"command":46},"npx","npx skills add Solizardking\u002Ftrain2earn --skill jetson-customize-uphy",{"tool":48,"command":49},"bunx","bunx skills add Solizardking\u002Ftrain2earn --skill jetson-customize-uphy",{"tool":51,"command":52},"pnpm","pnpm dlx skills add Solizardking\u002Ftrain2earn --skill jetson-customize-uphy","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002FSKILL.md",true,[56,62,66,70,74,78,82],{"path":57,"resourceType":58,"resourceTypeDesc":59,"sizeBytes":60,"sourceHtmlUrl":61},"BENCHMARK.md","REFERENCE","参考文档",3835,"https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002FBENCHMARK.md",{"path":63,"resourceType":58,"resourceTypeDesc":59,"sizeBytes":64,"sourceHtmlUrl":65},"evals\u002Fevals.json",4618,"https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002Fevals\u002Fevals.json",{"path":67,"resourceType":58,"resourceTypeDesc":59,"sizeBytes":68,"sourceHtmlUrl":69},"references\u002Fgotchas.md",1727,"https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002Freferences\u002Fgotchas.md",{"path":71,"resourceType":58,"resourceTypeDesc":59,"sizeBytes":72,"sourceHtmlUrl":73},"references\u002Fprocedure.md",17800,"https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002Freferences\u002Fprocedure.md",{"path":75,"resourceType":58,"resourceTypeDesc":59,"sizeBytes":76,"sourceHtmlUrl":77},"references\u002Frun-state-sidecar.md",1779,"https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002Freferences\u002Frun-state-sidecar.md",{"path":79,"resourceType":58,"resourceTypeDesc":59,"sizeBytes":80,"sourceHtmlUrl":81},"skill-card.md",3828,"https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002Fskill-card.md",{"path":83,"resourceType":84,"resourceTypeDesc":85,"sizeBytes":86,"sourceHtmlUrl":87},"skill.oms.sig","OTHER","其他",5309,"https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fnvidia\u002Fjetson-customize-uphy\u002Fskill.oms.sig",[89,97,105,113,120,128],{"skillNo":90,"name":91,"nameZh":6,"description":92,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":93,"licenseFileUrl":6,"sourceHtmlUrl":94,"categories":95,"keywords":96,"publishedAt":19},"01M78B94RSCAKMH1QS79VE6DG9","testing","For testing with Light Protocol programs and clients on localnet, devnet, and mainnet validation.","MIT","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Ftesting\u002FSKILL.md",[],[],{"skillNo":98,"name":99,"nameZh":6,"description":100,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":93,"licenseFileUrl":101,"sourceHtmlUrl":102,"categories":103,"keywords":104,"publishedAt":19},"01M78B81BKY8RX12HETPG8YKWK","qedgen","Formally verify programs by writing Lean 4 proofs. Trigger this skill whenever the user wants to formally verify code, generate Lean 4 proofs, prove properties about algorithms or smart contracts, verify invariants, convert program logic into formal specifications, or anything involving Lean 4 and formal verification. Also trigger when the user mentions \"qedgen\", \"lean proof\", \"formal proof\", \"verify my code\", \"prove correctness\", \"formal verification\", or wants mathematical guarantees about their implementation.","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fsolana-formal-verification\u002FLICENSE","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fsolana-formal-verification\u002FSKILL.md",[],[],{"skillNo":106,"name":107,"nameZh":6,"description":108,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":93,"licenseFileUrl":109,"sourceHtmlUrl":110,"categories":111,"keywords":112,"publishedAt":19},"01M78B7Q7C5K54E01DN83A60KG","solana-dev","Use when user asks to \"build a Solana dapp\", \"write an Anchor program\", \"create a token\", \"debug Solana errors\", \"set up wallet connection\", \"test my Solana program\", \"deploy to devnet\", or \"explain Solana concepts\" (rent, accounts, PDAs, CPIs, etc.). Also use for quick on-chain lookups via public RPC + curl — \"what's the balance of \u003Cwallet>\", \"look up transaction \u003Csig>\", \"token balance for \u003Caccount>\", \"check this address on mainnet\u002Fdevnet\". End-to-end Solana development playbook covering wallet connection, Anchor\u002FPinocchio programs, Codama client generation, LiteSVM\u002FMollusk\u002FSurfpool testing, security checklists, and JSON-RPC curl lookups against public clusters. Integrates with the Solana MCP server for live documentation search. Prefers framework-kit (@solana\u002Fclient + @solana\u002Freact-hooks) for UI, wallet-standard-first connection (incl. ConnectorKit), @solana\u002Fkit for client\u002FRPC code, and @solana\u002Fweb3-compat for legacy boundaries.","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fsolana-dev\u002FLICENSE","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fsolana-dev\u002FSKILL.md",[],[],{"skillNo":114,"name":115,"nameZh":6,"description":116,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":93,"licenseFileUrl":6,"sourceHtmlUrl":117,"categories":118,"keywords":119,"publishedAt":19},"01M78B7HXD6N6GWKSVRQ8F6Q31","solana-common-errors","Diagnose and fix common Solana development errors — GLIBC mismatches, Anchor version conflicts, cargo build-sbf \u002F platform-tools failures, LiteSVM issues, edition2024 crate pins, RPC airdrops, and Anchor 0.29→0.32 migrations. Use when builds fail, Anchor CLI won't install, or CI breaks on Debian\u002FUbuntu.","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fsolana-common-errors\u002FSKILL.md",[],[],{"skillNo":121,"name":122,"nameZh":6,"description":123,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":124,"sourceHtmlUrl":125,"categories":126,"keywords":127,"publishedAt":19},"01M78B6T7YSYWQ0N4DP40QDXEZ","skill-creator","Create or update AgentSkills. Use when designing, structuring, or packaging skills with scripts, references, and assets.","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fskill-creator\u002Flicense.txt","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fskill-creator\u002FSKILL.md",[],[],{"skillNo":129,"name":130,"nameZh":6,"description":131,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":93,"licenseFileUrl":6,"sourceHtmlUrl":132,"categories":133,"keywords":134,"publishedAt":19},"01M78B1VFT9X5AND7AE1HZPZGF","phantom-wallet-mcp","Execute wallet operations through the Phantom MCP server. Use when the user wants to interact with their Phantom wallet directly — get addresses, transfer SOL or SPL tokens, buy\u002Fswap tokens, sign transactions, and sign messages across Solana, Ethereum, Bitcoin, and Sui. Requires the @phantom\u002Fmcp-server to be configured as an MCP server.","https:\u002F\u002Fgithub.com\u002FSolizardking\u002Ftrain2earn\u002Fblob\u002Fmain\u002Fskillhub\u002Fskills\u002Fphantom-wallet-mcp\u002FSKILL.md",[],[]]