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Use for headless or no-camera Jetson deployments; not for CPU\u002FGPU frequency tuning.","pattanation\u002FNorvik","pattanation","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F235419268?v=4","01M71M5THHYYB15ME8R2E4FCZG","Patta","01M71M5TJM1NDM992M8PDKYR2K",0,"Apache-2.0","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-optimize-memory\u002FSKILL.md",[],[19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35],"jetson optimize memory","optimize","memory","camera","public","tuning","CPU","gpu","across","team","Frequency","use","unused","deployments","kernel","for","headless","2026-11-10 10:56:23",false,"---\nname: jetson-optimize-memory\ndescription: >-\n  Reclaim DRAM by disabling unused subsystems across MB1 BCT, MB2 BCT,\n  kernel reserved-memory, and SWIOTLB. Use for headless or no-camera\n  Jetson deployments; not for CPU\u002FGPU frequency tuning.\n\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nargument-hint: \"headless | no-camera | swiotlb\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - memory\n    - dram\n    - carveout\n    - swiotlb\n  domain: memory\n---\n\n# jetson-optimize-memory\n\nMemory is reserved across four layers ordered by boot chronology\n(higher row = earlier in boot, closer to hardware):\n\n| Layer | Content | Key files |\n|---|---|---|\n| MB1 BCT | firmware carveouts | per-module misc DTS |\n| MB2 BCT | firmware loading + AST controls | per-module misc DTS |\n| Kernel DTS | reserved-memory and driver binding | per-module DTS |\n| SWIOTLB | DMA bounce pool size | `\u003Cmodule>.conf.common` (`CMDLINE_ADD`) |\n\n**Critical rules:**\n\n- Only the scenarios in **Scenario recipes** are validated. Refuse any\n  request to disable a carveout\u002Fcluster\u002Fnode not in that table.\n- **Zeroing a carveout requires both: disabling the cluster's loading\n  controls AND removing the AST that references it.**\n- **Emit explicit overrides for every cluster in the recipe**, regardless\n  of how the source `#ifdef`\u002F`#else` looks. Verify the merged binary.\n- **GPU SW stack must match the chip**: T234 -> nvgpu, T264 and later\n  -> OpenRM. Follow the shared derived-platform rule in\n  `target-platform-contract.md`; stop on mismatches instead of guessing.\n- Do not set SWIOTLB to 0 — some peripherals can't use the IOMMU.\n\n---\n\n## Scenario recipes\n\n| Keyword | MB1 BCT carveouts | MB2 BCT | Kernel DTS |\n|---|---|---|---|\n| `headless` | DCE-family (see chip table) | DCE `auxp_controls` + DCE AST(s) | `display@\u003Caddr>` (and `dce@\u003Caddr>` if exposed) → disabled |\n| `no-camera` | RCE\u002FVI\u002FISP-family | RCE `auxp_controls` (each instance) + RCE AST(s) | recommended: VI\u002FISP\u002FNVCSI → disabled |\n\n### Chip-specific carveouts\n\n| Scenario | T234 (Orin) | T264 (Thor) |\n|---|---|---|\n| `headless` | `CARVEOUT_BPMP_DCE`, `CARVEOUT_DCE`, `CARVEOUT_DCE_TSEC`, `CARVEOUT_TSEC_DCE`, `CARVEOUT_DISP_EARLY_BOOT_FB` | `CARVEOUT_DCE`, `CARVEOUT_TSEC_DCE`, `CARVEOUT_HPSE_DCE`, `CARVEOUT_DISP_EARLY_BOOT_FB` |\n| `no-camera` | `CARVEOUT_RCE`, `CARVEOUT_CAMERA_TASKLIST` | `CARVEOUT_RCE`, `CARVEOUT_RCE1`, `CARVEOUT_RCE_RW`, `CARVEOUT_VI_TASKLIST`, `CARVEOUT_VI1_TASKLIST`, `CARVEOUT_ISP_TASKLIST`, `CARVEOUT_ISP1_TASKLIST` |\n\n> **Post-boot:** `headless` → `sudo systemctl set-default multi-user.target`.\n\n---\n\n## MB1 BCT carveout overrides\n\nFile: `Linux_for_Tegra\u002Fbootloader\u002Fgeneric\u002FBCT\u002Ftegra\u003Cchip>-mb1-bct-misc-\u003Cmodule>.dts`\n(e.g. `tegra234-mb1-bct-misc-p3767-0000.dts` for Orin Nano,\n`tegra264-mb1-bct-misc-p3834-0008-p4071-0000.dts` for Thor).\n\nFor each carveout, add inside the existing `carveout` node:\n\n```dts\naux_info@\u003CCARVEOUT_NAME> {\n    pref_base = \u003C0x0 0x0>;\n    size      = \u003C0x0 0x0>;\n    alignment = \u003C0x0 0x0>;\n};\n```\n\n---\n\n## MB2 BCT cluster + AST overrides\n\nFile: `Linux_for_Tegra\u002Fbootloader\u002Fgeneric\u002FBCT\u002Ftegra\u003Cchip>-mb2-bct-misc-\u003Cmodule>.dts`\n(includes `tegra\u003Cchip>-mb2-bct-common.dtsi`).\n\nFor each target cluster:\n\n1. Override `auxp_controls@\u003Cindex>`:\n   ```dts\n   auxp_controls@\u003Cindex> {\n       enable_init    = \u003C0>;\n       enable_fw_load = \u003C0>;\n       enable_unhalt  = \u003C0>;\n   };\n   ```\n2. `\u002Fdelete-node\u002F auxp_ast_config@\u003Cidx>;`\n\nLook up indices in `common.dtsi`: `auxp_controls@N` carries a comment\nnaming its cluster; `auxp_ast_config@N` has `ast_region` children whose\n`carveout = \u003CCARVEOUT_…>;` lines identify the owner.\n\n---\n\n## Kernel DT reserved-memory\n\n```sh\nDTB=Linux_for_Tegra\u002Fkernel\u002Fdtb\u002F\u003Cplatform-dtb-name>.dtb\ndtc -I dtb -O dts -o \u002Ftmp\u002Fplatform.dts $DTB\n# edit: status = \"disabled\" on target nodes\ndtc -I dts -O dtb -o $DTB \u002Ftmp\u002Fplatform.dts\n```\n\n**Display** — disable `display@\u003Caddr>`, plus `dce@\u003Caddr>` if exposed as\na separate kernel node.\n\n**Camera** — under `host1x@\u003Caddr>`, disable whichever of `vi*` \u002F `isp*`\n\u002F `nvcsi` exist on the BSP (only emit present nodes):\n\nLocate the display controller node in the decompiled DTS and disable it.\nThe node's unit address is chip-specific — find it by `compatible` string\n(e.g. `nvidia,tegra234-display`) rather than hard-coding the address.\n\n```dts\nhost1x@\u003Caddr> {\n    vi0@\u003Caddr>   { status = \"disabled\"; };\n    vi1@\u003Caddr>   { status = \"disabled\"; };\n    isp@\u003Caddr>   { status = \"disabled\"; };\n    isp1@\u003Caddr>  { status = \"disabled\"; };\n    nvcsi@\u003Caddr> { status = \"disabled\"; };\n};\n```\n\n---\n\n## SWIOTLB DMA bounce pool\n\nThe NVIDIA IOMMU covers peripheral DMA, so SWIOTLB is rarely used.\nEdit `CMDLINE_ADD` (**never** `CMDLINE`) in `Linux_for_Tegra\u002F\u003Cmodule>.conf.common`:\n\n```sh\n# Total bytes = swiotlb_value × 2048; 4 MiB pool:\nCMDLINE_ADD=\"... swiotlb=2048\"\n```\n\n---\n\n## Override verification (mandatory)\n\nAfter every patched MB1\u002FMB2 BCT `.dts`, reproduce the BSP's compile +\ndecompile using the same `-D…` flags from `bct_flags.append(...)` in\n`bootloader\u002Ftegraflash_impl_t\u003Cchip>.py`:\n\n```sh\ngcc -E -nostdinc -x assembler-with-cpp \\\n    -DENABLE_\u003CFLAG_1> -DENABLE_\u003CFLAG_2> \\\n    -I bootloader -I bootloader\u002Fgeneric\u002FBCT \\\n    -o \u002Ftmp\u002Fcpp.dts \u003Cpatched-bct.dts>\ndtc -q -I dts -O dtb -o \u002Ftmp\u002Fcpp.dtb \u002Ftmp\u002Fcpp.dts\ndtc -q -I dtb -O dts \u002Ftmp\u002Fcpp.dtb | less\n```\n\nConfirm in the merged output:\n- Each zeroed `aux_info@\u003CNAME>` (or `aux_info@\u003Cid>U` post macro expansion)\n  has `size = \u003C0x0 0x0>` and `pref_base = \u003C0x0 0x0>`.\n- Each disabled `auxp_controls@\u003Cidx>` has all three `enable_*` fields `\u003C0>`.\n- Each `\u002Fdelete-node\u002F`'d `auxp_ast_config@\u003Cidx>` is absent.\n\n---\n\n## Verification (on booted target)\n\n```sh\nsudo cat \u002Fproc\u002Fiomem | grep -iE 'nv-reserved|cma|fb|carveout'\nls \u002Fproc\u002Fdevice-tree\u002Freserved-memory\u002F\ndmesg | grep -iE 'firmware|carveout|bpmp|reserved|fail|error' | head -20\nfree -m\n```\n\n| Scenario | Sysfs | dmesg grep |\n|---|---|---|\n| Display off | `ls \u002Fsys\u002Fclass\u002Fdrm\u002F` (empty) | `tegra-drm\\|nvdisplay\\|dce\\|host1x\\|fb0` |\n| Camera off | `ls \u002Fdev\u002Fvideo* 2>\u002Fdev\u002Fnull` (none) | `rce\\|nvcsi\\|tegra-camera\\|vi0\\|vi1\\|isp` |\n| SWIOTLB shrink | `cat \u002Fsys\u002Fkernel\u002Fdebug\u002Fswiotlb\u002Fio_tlb_nslabs` matches cmdline | `swiotlb` |\n\nFor SWIOTLB: `\u002Fproc\u002Fcmdline` must contain `swiotlb=\u003Cvalue>`, and\n`watch -n5 cat \u002Fsys\u002Fkernel\u002Fdebug\u002Fswiotlb\u002Fio_tlb_used` must stay under\n`io_tlb_nslabs` during full workload — if exceeded, restore original\n`CMDLINE_ADD` and re-flash `kernel-dtb`.\n\n## Purpose\n\nCut the unused DRAM carveouts that ship enabled in the reference BSP\nwhen a Jetson deployment skips display, camera, or other peripherals,\nfreeing the freed bytes for the application. Always edits the four\nlayers in boot order so an early-stage carveout never outranks a\nlater-stage shrink.\n\n## Prerequisites\n\n- Active target profile resolved per\n  `..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md`.\n- BSP image extracted and source tree initialized\n  (`\u002Fjetson-init-image`, `\u002Fjetson-init-source` complete).\n- For headless \u002F no-camera recipes: confirm the workload truly does not\n  need display or camera.\n\n## Limitations\n\n- Only the validated recipes (`headless`, `no-camera`, `swiotlb`) are\n  exposed; ad-hoc subsystem disables outside the recipe set are\n  refused.\n- SWIOTLB shrink is bounded by peak in-flight DMA — exceeding the new\n  `io_tlb_nslabs` requires reverting the change.\n- BPMP-DTB edits land in the overlay tracker only after Customize +\n  Build + Deploy run; this skill does not flash on its own.\n\n## Troubleshooting\n\n- **Boot fails after MB1 BCT carveout disable** — restore the pristine\n  misc DTS and re-flash; the missing carveout is mandatory for the\n  active SoC.\n- **`io_tlb_used` exceeds `io_tlb_nslabs`** — revert `swiotlb=` in\n  `CMDLINE_ADD` and re-flash the kernel DTB partition.\n- **Reclaimed delta smaller than expected** — verify the recipe truly\n  matched the deployment (e.g. display still attached); use the\n  `dmesg | grep -iE 'firmware|carveout'` check in this file to confirm.\n- **Validation `dmesg` shows the disabled subsystem still probing** —\n  the change probably did not promote through to `bsp_image`; re-run\n  `\u002Fjetson-promote-image`.\n\n---\n","# jetson-optimize-memory\n\nMemory is reserved across four layers ordered by boot chronology\n(higher row = earlier in boot, closer to hardware):\n\n| Layer | Content | Key files |\n|---|---|---|\n| MB1 BCT | firmware carveouts | per-module misc DTS |\n| MB2 BCT | firmware loading + AST controls | per-module misc DTS |\n| Kernel DTS | reserved-memory and driver binding | per-module DTS |\n| SWIOTLB | DMA bounce pool size | `\u003Cmodule>.conf.common` (`CMDLINE_ADD`) |\n\n**Critical rules:**\n\n- Only the scenarios in **Scenario recipes** are validated. Refuse any\n  request to disable a carveout\u002Fcluster\u002Fnode not in that table.\n- **Zeroing a carveout requires both: disabling the cluster's loading\n  controls AND removing the AST that references it.**\n- **Emit explicit overrides for every cluster in the recipe**, regardless\n  of how the source `#ifdef`\u002F`#else` looks. Verify the merged binary.\n- **GPU SW stack must match the chip**: T234 -> nvgpu, T264 and later\n  -> OpenRM. Follow the shared derived-platform rule in\n  `target-platform-contract.md`; stop on mismatches instead of guessing.\n- Do not set SWIOTLB to 0 — some peripherals can't use the IOMMU.\n\n---\n\n## Scenario recipes\n\n| Keyword | MB1 BCT carveouts | MB2 BCT | Kernel DTS |\n|---|---|---|---|\n| `headless` | DCE-family (see chip table) | DCE `auxp_controls` + DCE AST(s) | `display@\u003Caddr>` (and `dce@\u003Caddr>` if exposed) → disabled |\n| `no-camera` | RCE\u002FVI\u002FISP-family | RCE `auxp_controls` (each instance) + RCE AST(s) | recommended: VI\u002FISP\u002FNVCSI → disabled |\n\n### Chip-specific carveouts\n\n| Scenario | T234 (Orin) | T264 (Thor) |\n|---|---|---|\n| `headless` | `CARVEOUT_BPMP_DCE`, `CARVEOUT_DCE`, `CARVEOUT_DCE_TSEC`, `CARVEOUT_TSEC_DCE`, `CARVEOUT_DISP_EARLY_BOOT_FB` | `CARVEOUT_DCE`, `CARVEOUT_TSEC_DCE`, `CARVEOUT_HPSE_DCE`, `CARVEOUT_DISP_EARLY_BOOT_FB` |\n| `no-camera` | `CARVEOUT_RCE`, `CARVEOUT_CAMERA_TASKLIST` | `CARVEOUT_RCE`, `CARVEOUT_RCE1`, `CARVEOUT_RCE_RW`, `CARVEOUT_VI_TASKLIST`, `CARVEOUT_VI1_TASKLIST`, `CARVEOUT_ISP_TASKLIST`, `CARVEOUT_ISP1_TASKLIST` |\n\n> **Post-boot:** `headless` → `sudo systemctl set-default multi-user.target`.\n\n---\n\n## MB1 BCT carveout overrides\n\nFile: `Linux_for_Tegra\u002Fbootloader\u002Fgeneric\u002FBCT\u002Ftegra\u003Cchip>-mb1-bct-misc-\u003Cmodule>.dts`\n(e.g. `tegra234-mb1-bct-misc-p3767-0000.dts` for Orin Nano,\n`tegra264-mb1-bct-misc-p3834-0008-p4071-0000.dts` for Thor).\n\nFor each carveout, add inside the existing `carveout` node:\n\n```dts\naux_info@\u003CCARVEOUT_NAME> {\n    pref_base = \u003C0x0 0x0>;\n    size      = \u003C0x0 0x0>;\n    alignment = \u003C0x0 0x0>;\n};\n```\n\n---\n\n## MB2 BCT cluster + AST overrides\n\nFile: `Linux_for_Tegra\u002Fbootloader\u002Fgeneric\u002FBCT\u002Ftegra\u003Cchip>-mb2-bct-misc-\u003Cmodule>.dts`\n(includes `tegra\u003Cchip>-mb2-bct-common.dtsi`).\n\nFor each target cluster:\n\n1. Override `auxp_controls@\u003Cindex>`:\n   ```dts\n   auxp_controls@\u003Cindex> {\n       enable_init    = \u003C0>;\n       enable_fw_load = \u003C0>;\n       enable_unhalt  = \u003C0>;\n   };\n   ```\n2. `\u002Fdelete-node\u002F auxp_ast_config@\u003Cidx>;`\n\nLook up indices in `common.dtsi`: `auxp_controls@N` carries a comment\nnaming its cluster; `auxp_ast_config@N` has `ast_region` children whose\n`carveout = \u003CCARVEOUT_…>;` lines identify the owner.\n\n---\n\n## Kernel DT reserved-memory\n\n```sh\nDTB=Linux_for_Tegra\u002Fkernel\u002Fdtb\u002F\u003Cplatform-dtb-name>.dtb\ndtc -I dtb -O dts -o \u002Ftmp\u002Fplatform.dts $DTB\n# edit: status = \"disabled\" on target nodes\ndtc -I dts -O dtb -o $DTB \u002Ftmp\u002Fplatform.dts\n```\n\n**Display** — disable `display@\u003Caddr>`, plus `dce@\u003Caddr>` if exposed as\na separate kernel node.\n\n**Camera** — under `host1x@\u003Caddr>`, disable whichever of `vi*` \u002F `isp*`\n\u002F `nvcsi` exist on the BSP (only emit present nodes):\n\nLocate the display controller node in the decompiled DTS and disable it.\nThe node's unit address is chip-specific — find it by `compatible` string\n(e.g. `nvidia,tegra234-display`) rather than hard-coding the address.\n\n```dts\nhost1x@\u003Caddr> {\n    vi0@\u003Caddr>   { status = \"disabled\"; };\n    vi1@\u003Caddr>   { status = \"disabled\"; };\n    isp@\u003Caddr>   { status = \"disabled\"; };\n    isp1@\u003Caddr>  { status = \"disabled\"; };\n    nvcsi@\u003Caddr> { status = \"disabled\"; };\n};\n```\n\n---\n\n## SWIOTLB DMA bounce pool\n\nThe NVIDIA IOMMU covers peripheral DMA, so SWIOTLB is rarely used.\nEdit `CMDLINE_ADD` (**never** `CMDLINE`) in `Linux_for_Tegra\u002F\u003Cmodule>.conf.common`:\n\n```sh\n# Total bytes = swiotlb_value × 2048; 4 MiB pool:\nCMDLINE_ADD=\"... swiotlb=2048\"\n```\n\n---\n\n## Override verification (mandatory)\n\nAfter every patched MB1\u002FMB2 BCT `.dts`, reproduce the BSP's compile +\ndecompile using the same `-D…` flags from `bct_flags.append(...)` in\n`bootloader\u002Ftegraflash_impl_t\u003Cchip>.py`:\n\n```sh\ngcc -E -nostdinc -x assembler-with-cpp \\\n    -DENABLE_\u003CFLAG_1> -DENABLE_\u003CFLAG_2> \\\n    -I bootloader -I bootloader\u002Fgeneric\u002FBCT \\\n    -o \u002Ftmp\u002Fcpp.dts \u003Cpatched-bct.dts>\ndtc -q -I dts -O dtb -o \u002Ftmp\u002Fcpp.dtb \u002Ftmp\u002Fcpp.dts\ndtc -q -I dtb -O dts \u002Ftmp\u002Fcpp.dtb | less\n```\n\nConfirm in the merged output:\n- Each zeroed `aux_info@\u003CNAME>` (or `aux_info@\u003Cid>U` post macro expansion)\n  has `size = \u003C0x0 0x0>` and `pref_base = \u003C0x0 0x0>`.\n- Each disabled `auxp_controls@\u003Cidx>` has all three `enable_*` fields `\u003C0>`.\n- Each `\u002Fdelete-node\u002F`'d `auxp_ast_config@\u003Cidx>` is absent.\n\n---\n\n## Verification (on booted target)\n\n```sh\nsudo cat \u002Fproc\u002Fiomem | grep -iE 'nv-reserved|cma|fb|carveout'\nls \u002Fproc\u002Fdevice-tree\u002Freserved-memory\u002F\ndmesg | grep -iE 'firmware|carveout|bpmp|reserved|fail|error' | head -20\nfree -m\n```\n\n| Scenario | Sysfs | dmesg grep |\n|---|---|---|\n| Display off | `ls \u002Fsys\u002Fclass\u002Fdrm\u002F` (empty) | `tegra-drm\\|nvdisplay\\|dce\\|host1x\\|fb0` |\n| Camera off | `ls \u002Fdev\u002Fvideo* 2>\u002Fdev\u002Fnull` (none) | `rce\\|nvcsi\\|tegra-camera\\|vi0\\|vi1\\|isp` |\n| SWIOTLB shrink | `cat \u002Fsys\u002Fkernel\u002Fdebug\u002Fswiotlb\u002Fio_tlb_nslabs` matches cmdline | `swiotlb` |\n\nFor SWIOTLB: `\u002Fproc\u002Fcmdline` must contain `swiotlb=\u003Cvalue>`, and\n`watch -n5 cat \u002Fsys\u002Fkernel\u002Fdebug\u002Fswiotlb\u002Fio_tlb_used` must stay under\n`io_tlb_nslabs` during full workload — if exceeded, restore original\n`CMDLINE_ADD` and re-flash `kernel-dtb`.\n\n## Purpose\n\nCut the unused DRAM carveouts that ship enabled in the reference BSP\nwhen a Jetson deployment skips display, camera, or other peripherals,\nfreeing the freed bytes for the application. Always edits the four\nlayers in boot order so an early-stage carveout never outranks a\nlater-stage shrink.\n\n## Prerequisites\n\n- Active target profile resolved per\n  `..\u002F..\u002Fcontext\u002Ftarget-platform-contract.md`.\n- BSP image extracted and source tree initialized\n  (`\u002Fjetson-init-image`, `\u002Fjetson-init-source` complete).\n- For headless \u002F no-camera recipes: confirm the workload truly does not\n  need display or camera.\n\n## Limitations\n\n- Only the validated recipes (`headless`, `no-camera`, `swiotlb`) are\n  exposed; ad-hoc subsystem disables outside the recipe set are\n  refused.\n- SWIOTLB shrink is bounded by peak in-flight DMA — exceeding the new\n  `io_tlb_nslabs` requires reverting the change.\n- BPMP-DTB edits land in the overlay tracker only after Customize +\n  Build + Deploy run; this skill does not flash on its own.\n\n## Troubleshooting\n\n- **Boot fails after MB1 BCT carveout disable** — restore the pristine\n  misc DTS and re-flash; the missing carveout is mandatory for the\n  active SoC.\n- **`io_tlb_used` exceeds `io_tlb_nslabs`** — revert `swiotlb=` in\n  `CMDLINE_ADD` and re-flash the kernel DTB partition.\n- **Reclaimed delta smaller than expected** — verify the recipe truly\n  matched the deployment (e.g. display still attached); use the\n  `dmesg | grep -iE 'firmware|carveout'` check in this file to confirm.\n- **Validation `dmesg` shows the disabled subsystem still probing** —\n  the change probably did not promote through to `bsp_image`; re-run\n  `\u002Fjetson-promote-image`.\n\n---\n",{"name":5,"license":15,"version":41,"metadata":42,"description":7,"argument-hint":48},"0.0.1",{"tags":43,"author":47,"domain":21,"data-classification":23},[21,44,45,46],"dram","carveout","swiotlb","Jetson Team","headless | no-camera | swiotlb","claude\u002Finstall-gsd-build-foQdV","d86cd127f527124b5fd0fd0bc679a4d79b7d01d7",".agents\u002Fskills\u002Fjetson-optimize-memory","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik","https:\u002F\u002Fnorvik-orpin.vercel.app","https:\u002F\u002Fgithub.com\u002Fpattanation","2026-07-17 11:17:04",{"source":8,"skillName":5,"commands":57,"prompt":67,"zipAvailable":68},[58,61,64],{"tool":59,"command":60},"npx","npx skills add pattanation\u002FNorvik --skill jetson-optimize-memory",{"tool":62,"command":63},"bunx","bunx skills add pattanation\u002FNorvik --skill jetson-optimize-memory",{"tool":65,"command":66},"pnpm","pnpm dlx skills add pattanation\u002FNorvik --skill jetson-optimize-memory","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-optimize-memory\u002FSKILL.md",true,[70,76,80,84],{"path":71,"resourceType":72,"resourceTypeDesc":73,"sizeBytes":74,"sourceHtmlUrl":75},"BENCHMARK.md","REFERENCE","参考文档",3839,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-optimize-memory\u002FBENCHMARK.md",{"path":77,"resourceType":72,"resourceTypeDesc":73,"sizeBytes":78,"sourceHtmlUrl":79},"evals\u002Fevals.json",4924,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-optimize-memory\u002Fevals\u002Fevals.json",{"path":81,"resourceType":72,"resourceTypeDesc":73,"sizeBytes":82,"sourceHtmlUrl":83},"skill-card.md",3704,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-optimize-memory\u002Fskill-card.md",{"path":85,"resourceType":86,"resourceTypeDesc":87,"sizeBytes":88,"sourceHtmlUrl":89},"skill.oms.sig","OTHER","其他",4597,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-optimize-memory\u002Fskill.oms.sig",[91,124,149,173,195,210],{"skillNo":92,"name":93,"nameZh":6,"description":94,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":95,"sourceHtmlUrl":96,"categories":97,"keywords":106,"publishedAt":123},"01M71QDV4DM8T19HEHWATEF1K4","webapp-testing","Toolkit for interacting with and testing local web applications using Playwright. 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