[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M71NKB119NHSEVQB2S34Q2K9":3,"skill-same:01M71NKB119NHSEVQB2S34Q2K9":115},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":38,"linkOnly":39,"markdownContent":40,"markdownBody":41,"frontMatter":42,"refName":50,"commitSha":51,"skillDirectory":52,"forksCount":14,"repositoryHtmlUrl":53,"repositoryHomepageUrl":54,"ownerHtmlUrl":55,"ownerBlogUrl":6,"ownerDescription":6,"updatedAt":56,"install":57,"resources":70},"01M71NKB119NHSEVQB2S34Q2K9","jetson-customize-usb",null,"Enable\u002Fdisable Jetson USB2\u002FUSB3 SS ports via kernel-DT overlay. Do NOT use for UPHY lane allocation or ODMDATA edits.","pattanation\u002FNorvik","pattanation","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F235419268?v=4","01M71M5THHYYB15ME8R2E4FCZG","Patta","01M71M5TJM1NDM992M8PDKYR2K",0,"Apache-2.0","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-usb\u002FSKILL.md",[],[19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37],"customize","jetson customize usb","usb","Meta","team","ports","public","use","do","io","via","ss","lane","allocation","for","overlay","phase","disable","kernel","2026-11-10 10:56:23",false,"---\nname: jetson-customize-usb\ndescription: Enable\u002Fdisable Jetson USB2\u002FUSB3 SS ports via kernel-DT overlay. Do NOT use for UPHY lane allocation or ODMDATA edits.\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - bsp\n    - phase-2\n    - io\n    - usb\n  domain: meta\n---\n\n# Customize USB (per-port enable \u002F disable \u002F role)\n\n## Purpose\n\nEnable, disable, or change the role of USB2 \u002F USB3 SS ports on a\nJetson Thor (Tegra264) or Orin (Tegra234) custom carrier. Captures\nper-port wiring (role, max speed, VBUS-EN \u002F OC GPIOs, CC1\u002FCC2 GPIOs\nfor Type-C, USB3 SS UPHY lane), resolves the SS to USB2 companion\ngraph from the in-tree DTB, then renders a self-contained kernel-DT\noverlay that flips every port action in three places in lockstep\n(lane status, port status, host xHCI `phys` + `phy-names`).\n\nUPHY lane allocation belongs to `jetson-customize-uphy`. No ODMDATA\nedit. Output is one commit to the composite custom overlay `.dts` in\nthe `bsp_sources\u002F` hardware repo.\n\n## Prerequisites\n\n- Active profile with `reference_devkit:` + `custom_carrier:` blocks.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` exists\n  (`\u002Fjetson-init-source`).\n- `\u002Fjetson-derive-carrier` has run — carrier flash-conf fork in the\n  overlay tracker.\n- `\u002Fjetson-customize-uphy` has run when any enabled USB3 SS port\n  needs a non-stock UPHY lane allocation. Its JSON sidecar at\n  `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-uphy.json`\n  is consulted for SS lane allocation.\n- Source-of-truth docs: Adaptation Guide §\"Port the Universal Serial\n  Bus\", Module Design Guide §USB, SoC TRM (xusb block).\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** Refuse the run\n  if either is missing — per-port routing (VBUS-EN \u002F OC \u002F CC GPIOs, SS\n  lane wiring, hub fan-out) on a custom carrier cannot be guessed.\n  Reference-devkit-only profiles skip this check.\n- `dtc`, `fdtoverlay` on PATH.\n\n## Overview\n\nUSB on Tegra spans three IP surfaces: the `xusb_padctl` block (USB2\nOTG + USB3 SS PHYs), the `tegra-xusb` xHCI host controller, and an\noptional `tegra-xudc` device controller attached to the single\nOTG-capable USB2 port (`usb2-0`).\n\n**A per-port flip MUST touch three kernel-DT places in lockstep.**\nAnything less crashes the host xHCI probe and leaves `lsusb` empty\non every port (collateral damage to stock-okay ports):\n\n| # | Place | Path | What it controls |\n|---|---|---|---|\n| 1 | **Lane (PHY provider)** | `xusb_padctl\u002Fpads\u002Fusb\u003C2\\|3>\u002Flanes\u002Fusb\u003C2\\|3>-N` | SS \u002F OTG PHY hardware-binding. `status=\"disabled\"` then lane stops providing a PHY. |\n| 2 | **Port (controller-binding)** | `xusb_padctl\u002Fports\u002Fusb\u003C2\\|3>-N` | Per-port mode (host\u002Fdevice\u002Fotg), companion link, VBUS \u002F OC \u002F CC pin refs. `status=\"disabled\"` then port removed from user-facing topology. |\n| 3 | **Host xHCI phys-list** | `bus@0\u002Fusb@\u003Caddr>.phys` + `.phy-names` | Array of phandles + names the xHCI driver iterates. A ref to a disabled PHY returns `-ENODEV` and aborts the whole host probe. |\n\nNVIDIA's stock-disabled `usb3-3` in the Thor base DTB is the canonical\npattern — all three places flipped in lockstep.\n\n**Two extra rules ride on top of the three-place pattern:**\n\n- **Rule A — lane + port pairing.** Lane (place 1) and matching port\n  (place 2) MUST flip together.\n- **Rule B — companion cascade.**\n  `xusb_padctl\u002Fports\u002Fusb3-N.nvidia,usb2-companion` references a USB2\n  port phandle. Disabling that USB2 without cascading to its SS\n  companion then `tegra-xusb: failed to enable PHYs: -19`.\n\n**Agentic, not table-driven** — every port, controller, lane,\ncompanion link, phandle, and `__symbols__` lookup is resolved at\nruntime from docs + DTB + carrier pinmap + schematic.\n\n## When to invoke\n\n- The user says \"enable USB\", \"disable USB hub\", \"configure USB3 SS\",\n  \"set USB role\", \"wire VBUS-EN\", \"tegra-xusb \u002F xudc \u002F dr_mode\", or\n  asks to bring up \u002F take down a USB controller on a custom carrier.\n- A USB receptacle on the carrier doesn't enumerate after flash, OR\n  collateral USB damage (`lsusb` empty after a previous\n  jetson-customize-usb attempt) needs to be fixed.\n- `jetson-customize-uphy` re-allocated UPHY lanes affecting USB3 SS\n  ports and per-port DT now needs to follow.\n\n## Procedure (summary)\n\nThe full step-by-step procedure lives in `references\u002Fprocedure.md`.\n\n1. **Step 1** — resolve active target + open source-of-truth docs.\n2. **Step 2** — build the USB topology + companion graph from the\n   in-tree DTB.\n3. **Step 3** — `AskUserQuestion` for port(s) to enable \u002F disable;\n   surface companion cascade + on-carrier hub fan-out explicitly.\n4. **Step 4** — per-port verify (module + carrier + UPHY lane) and\n   capture wiring (VBUS-EN \u002F OC \u002F CC GPIOs via `pin_verifier.py`).\n5. **Step 5** — render the kernel-DT overlay using the three-place\n   pattern, append fragments (`usb:padctl`, `usb:xhci`, optional\n   `usb:xudc`) to the composite custom overlay `.dts`, run\n   `fdtoverlay` + the three post-merge invariants, commit to\n   `bsp_sources\u002F`.\n6. **Step 6** — write run-state JSON sidecar (shape in\n   `references\u002Frun-state-sidecar.md`), emit headline, then drive the\n   downstream next-step chain via sequential `AskUserQuestion` prompts\n   per `references\u002Fprocedure.md` Step 6. Never substitute a printed\n   \"Next step: …\" line for the prompts.\n\nSee `references\u002Fgotchas.md` for the load-bearing failure modes.\n\n## Limitations\n\n- Owns kernel-DT overlay only. ODMDATA does not expose a per-port\n  USB `status` knob; do not edit it.\n- Does NOT allocate UPHY lanes — `jetson-customize-uphy` owns that.\n  Refuse to commit an SS-enable until uphy run-state shows the lane\n  allocated.\n- Does NOT directly patch the pinmux DTSI — routes SFIO mismatches\n  to `\u002Fjetson-customize-pinmux set-pin`.\n- Does NOT compile the `.dtbo` or register `OVERLAY_DTB_FILE+=` —\n  `\u002Fjetson-build-source` owns build + flash-conf registration.\n- Tegra platform invariant: only `usb2-0` is OTG-capable; `xudc`\n  attaches there only. All other USB2 ports and all USB3 SS ports\n  are host-only.\n\n## Troubleshooting\n\n- **Empty `lsusb` on every port, USB-eth at 192.168.55.1 still up:**\n  host xHCI bailed; three-place lockstep was broken. Inspect merged\n  DTB; verify post-merge invariants in `references\u002Fprocedure.md`\n  Step 5d.\n- **`tegra-xusb: failed to enable PHYs: -19`:** companion cascade\n  (Rule B) violated — a USB2 was disabled without its SS companion.\n- **`no port found` or `Requested PHY is disabled`:** Rule A\n  violated — lane status and port status are mismatched.\n- **`FDT_ERR_NOTFOUND` from `fdtoverlay`:** a fragment used\n  `target = \u003C&label>` for a node whose label is not in\n  `__symbols__` (typical for host xHCI \u002F `tegra-xudc`). Switch to\n  `target-path = \"\u002Fbus@0\u002Fusb@\u003Caddr>\"`.\n- **dtc warning `phys_property: cell 0 is not a phandle reference`:**\n  benign; expected when using raw integer phandles in the host phys\n  override.\n- **Port boots but VBUS never asserts:** `vbus-supply` references a\n  regulator parent node that does not exist. Ensure the fixed\n  regulator node is present before referencing it.\n- **xHCI binds the wrong port at boot:** host `phys` element order\n  was not preserved. Only elide disabled entries; never reorder\n  kept ones.\n\n## References\n\n- `references\u002Fprocedure.md` — full step-by-step procedure.\n- `references\u002Fgotchas.md` — load-bearing failure modes.\n- `references\u002Frun-state-sidecar.md` — run-state JSON shape.\n- `references\u002Fusb-architecture.md` — Tegra USB IP architecture\n  notes (`xusb_padctl`, `tegra-xusb`, `xudc`).\n- `references\u002Fusb-dt-bindings.md` — USB DT binding cheatsheet\n  (lane \u002F port \u002F phys-list shapes).\n- `..\u002F..\u002Fscripts\u002Fpin_verifier.py` — shared HSIO pin verifier.\n- `..\u002F..\u002Freferences\u002Fplatform_template.yaml` — `documents:` block\n  consumed by Step 1.\n- `..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md` — overlay edit\n  protocol.\n- `..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md` — composite\n  overlay append protocol.\n- `..\u002Fjetson-customize-uphy\u002FSKILL.md` — sibling skill that owns\n  UPHY lane allocation.\n- `..\u002Fjetson-customize-pinmux\u002FSKILL.md` — sibling skill for\n  VBUS-EN \u002F OC \u002F CC SFIO fixes.\n- `..\u002Fjetson-derive-carrier\u002FSKILL.md` — must run first.\n- `..\u002Fjetson-init-source\u002FSKILL.md` — produces the overlay tracker\n  + `bsp_sources` repo.\n","# Customize USB (per-port enable \u002F disable \u002F role)\n\n## Purpose\n\nEnable, disable, or change the role of USB2 \u002F USB3 SS ports on a\nJetson Thor (Tegra264) or Orin (Tegra234) custom carrier. Captures\nper-port wiring (role, max speed, VBUS-EN \u002F OC GPIOs, CC1\u002FCC2 GPIOs\nfor Type-C, USB3 SS UPHY lane), resolves the SS to USB2 companion\ngraph from the in-tree DTB, then renders a self-contained kernel-DT\noverlay that flips every port action in three places in lockstep\n(lane status, port status, host xHCI `phys` + `phy-names`).\n\nUPHY lane allocation belongs to `jetson-customize-uphy`. No ODMDATA\nedit. Output is one commit to the composite custom overlay `.dts` in\nthe `bsp_sources\u002F` hardware repo.\n\n## Prerequisites\n\n- Active profile with `reference_devkit:` + `custom_carrier:` blocks.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` exists\n  (`\u002Fjetson-init-source`).\n- `\u002Fjetson-derive-carrier` has run — carrier flash-conf fork in the\n  overlay tracker.\n- `\u002Fjetson-customize-uphy` has run when any enabled USB3 SS port\n  needs a non-stock UPHY lane allocation. Its JSON sidecar at\n  `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-uphy.json`\n  is consulted for SS lane allocation.\n- Source-of-truth docs: Adaptation Guide §\"Port the Universal Serial\n  Bus\", Module Design Guide §USB, SoC TRM (xusb block).\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** Refuse the run\n  if either is missing — per-port routing (VBUS-EN \u002F OC \u002F CC GPIOs, SS\n  lane wiring, hub fan-out) on a custom carrier cannot be guessed.\n  Reference-devkit-only profiles skip this check.\n- `dtc`, `fdtoverlay` on PATH.\n\n## Overview\n\nUSB on Tegra spans three IP surfaces: the `xusb_padctl` block (USB2\nOTG + USB3 SS PHYs), the `tegra-xusb` xHCI host controller, and an\noptional `tegra-xudc` device controller attached to the single\nOTG-capable USB2 port (`usb2-0`).\n\n**A per-port flip MUST touch three kernel-DT places in lockstep.**\nAnything less crashes the host xHCI probe and leaves `lsusb` empty\non every port (collateral damage to stock-okay ports):\n\n| # | Place | Path | What it controls |\n|---|---|---|---|\n| 1 | **Lane (PHY provider)** | `xusb_padctl\u002Fpads\u002Fusb\u003C2\\|3>\u002Flanes\u002Fusb\u003C2\\|3>-N` | SS \u002F OTG PHY hardware-binding. `status=\"disabled\"` then lane stops providing a PHY. |\n| 2 | **Port (controller-binding)** | `xusb_padctl\u002Fports\u002Fusb\u003C2\\|3>-N` | Per-port mode (host\u002Fdevice\u002Fotg), companion link, VBUS \u002F OC \u002F CC pin refs. `status=\"disabled\"` then port removed from user-facing topology. |\n| 3 | **Host xHCI phys-list** | `bus@0\u002Fusb@\u003Caddr>.phys` + `.phy-names` | Array of phandles + names the xHCI driver iterates. A ref to a disabled PHY returns `-ENODEV` and aborts the whole host probe. |\n\nNVIDIA's stock-disabled `usb3-3` in the Thor base DTB is the canonical\npattern — all three places flipped in lockstep.\n\n**Two extra rules ride on top of the three-place pattern:**\n\n- **Rule A — lane + port pairing.** Lane (place 1) and matching port\n  (place 2) MUST flip together.\n- **Rule B — companion cascade.**\n  `xusb_padctl\u002Fports\u002Fusb3-N.nvidia,usb2-companion` references a USB2\n  port phandle. Disabling that USB2 without cascading to its SS\n  companion then `tegra-xusb: failed to enable PHYs: -19`.\n\n**Agentic, not table-driven** — every port, controller, lane,\ncompanion link, phandle, and `__symbols__` lookup is resolved at\nruntime from docs + DTB + carrier pinmap + schematic.\n\n## When to invoke\n\n- The user says \"enable USB\", \"disable USB hub\", \"configure USB3 SS\",\n  \"set USB role\", \"wire VBUS-EN\", \"tegra-xusb \u002F xudc \u002F dr_mode\", or\n  asks to bring up \u002F take down a USB controller on a custom carrier.\n- A USB receptacle on the carrier doesn't enumerate after flash, OR\n  collateral USB damage (`lsusb` empty after a previous\n  jetson-customize-usb attempt) needs to be fixed.\n- `jetson-customize-uphy` re-allocated UPHY lanes affecting USB3 SS\n  ports and per-port DT now needs to follow.\n\n## Procedure (summary)\n\nThe full step-by-step procedure lives in `references\u002Fprocedure.md`.\n\n1. **Step 1** — resolve active target + open source-of-truth docs.\n2. **Step 2** — build the USB topology + companion graph from the\n   in-tree DTB.\n3. **Step 3** — `AskUserQuestion` for port(s) to enable \u002F disable;\n   surface companion cascade + on-carrier hub fan-out explicitly.\n4. **Step 4** — per-port verify (module + carrier + UPHY lane) and\n   capture wiring (VBUS-EN \u002F OC \u002F CC GPIOs via `pin_verifier.py`).\n5. **Step 5** — render the kernel-DT overlay using the three-place\n   pattern, append fragments (`usb:padctl`, `usb:xhci`, optional\n   `usb:xudc`) to the composite custom overlay `.dts`, run\n   `fdtoverlay` + the three post-merge invariants, commit to\n   `bsp_sources\u002F`.\n6. **Step 6** — write run-state JSON sidecar (shape in\n   `references\u002Frun-state-sidecar.md`), emit headline, then drive the\n   downstream next-step chain via sequential `AskUserQuestion` prompts\n   per `references\u002Fprocedure.md` Step 6. Never substitute a printed\n   \"Next step: …\" line for the prompts.\n\nSee `references\u002Fgotchas.md` for the load-bearing failure modes.\n\n## Limitations\n\n- Owns kernel-DT overlay only. ODMDATA does not expose a per-port\n  USB `status` knob; do not edit it.\n- Does NOT allocate UPHY lanes — `jetson-customize-uphy` owns that.\n  Refuse to commit an SS-enable until uphy run-state shows the lane\n  allocated.\n- Does NOT directly patch the pinmux DTSI — routes SFIO mismatches\n  to `\u002Fjetson-customize-pinmux set-pin`.\n- Does NOT compile the `.dtbo` or register `OVERLAY_DTB_FILE+=` —\n  `\u002Fjetson-build-source` owns build + flash-conf registration.\n- Tegra platform invariant: only `usb2-0` is OTG-capable; `xudc`\n  attaches there only. All other USB2 ports and all USB3 SS ports\n  are host-only.\n\n## Troubleshooting\n\n- **Empty `lsusb` on every port, USB-eth at 192.168.55.1 still up:**\n  host xHCI bailed; three-place lockstep was broken. Inspect merged\n  DTB; verify post-merge invariants in `references\u002Fprocedure.md`\n  Step 5d.\n- **`tegra-xusb: failed to enable PHYs: -19`:** companion cascade\n  (Rule B) violated — a USB2 was disabled without its SS companion.\n- **`no port found` or `Requested PHY is disabled`:** Rule A\n  violated — lane status and port status are mismatched.\n- **`FDT_ERR_NOTFOUND` from `fdtoverlay`:** a fragment used\n  `target = \u003C&label>` for a node whose label is not in\n  `__symbols__` (typical for host xHCI \u002F `tegra-xudc`). Switch to\n  `target-path = \"\u002Fbus@0\u002Fusb@\u003Caddr>\"`.\n- **dtc warning `phys_property: cell 0 is not a phandle reference`:**\n  benign; expected when using raw integer phandles in the host phys\n  override.\n- **Port boots but VBUS never asserts:** `vbus-supply` references a\n  regulator parent node that does not exist. Ensure the fixed\n  regulator node is present before referencing it.\n- **xHCI binds the wrong port at boot:** host `phys` element order\n  was not preserved. Only elide disabled entries; never reorder\n  kept ones.\n\n## References\n\n- `references\u002Fprocedure.md` — full step-by-step procedure.\n- `references\u002Fgotchas.md` — load-bearing failure modes.\n- `references\u002Frun-state-sidecar.md` — run-state JSON shape.\n- `references\u002Fusb-architecture.md` — Tegra USB IP architecture\n  notes (`xusb_padctl`, `tegra-xusb`, `xudc`).\n- `references\u002Fusb-dt-bindings.md` — USB DT binding cheatsheet\n  (lane \u002F port \u002F phys-list shapes).\n- `..\u002F..\u002Fscripts\u002Fpin_verifier.py` — shared HSIO pin verifier.\n- `..\u002F..\u002Freferences\u002Fplatform_template.yaml` — `documents:` block\n  consumed by Step 1.\n- `..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md` — overlay edit\n  protocol.\n- `..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md` — composite\n  overlay append protocol.\n- `..\u002Fjetson-customize-uphy\u002FSKILL.md` — sibling skill that owns\n  UPHY lane allocation.\n- `..\u002Fjetson-customize-pinmux\u002FSKILL.md` — sibling skill for\n  VBUS-EN \u002F OC \u002F CC SFIO fixes.\n- `..\u002Fjetson-derive-carrier\u002FSKILL.md` — must run first.\n- `..\u002Fjetson-init-source\u002FSKILL.md` — produces the overlay tracker\n  + `bsp_sources` repo.\n",{"name":5,"license":15,"version":43,"metadata":44,"description":7},"0.0.1",{"tags":45,"author":48,"domain":49,"data-classification":25},[46,47,28,21],"bsp","phase-2","Jetson Team","meta","claude\u002Finstall-gsd-build-foQdV","d86cd127f527124b5fd0fd0bc679a4d79b7d01d7",".agents\u002Fskills\u002Fjetson-customize-usb","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik","https:\u002F\u002Fnorvik-orpin.vercel.app","https:\u002F\u002Fgithub.com\u002Fpattanation","2026-07-17 11:17:04",{"source":8,"skillName":5,"commands":58,"prompt":68,"zipAvailable":69},[59,62,65],{"tool":60,"command":61},"npx","npx skills add pattanation\u002FNorvik --skill jetson-customize-usb",{"tool":63,"command":64},"bunx","bunx skills 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