[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M71NK35VDF55DWWK0G0X3HBA":3,"skill-same:01M71NK35VDF55DWWK0G0X3HBA":102},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":39,"linkOnly":40,"markdownContent":41,"markdownBody":42,"frontMatter":43,"refName":53,"commitSha":54,"skillDirectory":55,"forksCount":14,"repositoryHtmlUrl":56,"repositoryHomepageUrl":57,"ownerHtmlUrl":58,"ownerBlogUrl":6,"ownerDescription":6,"updatedAt":59,"install":60,"resources":73},"01M71NK35VDF55DWWK0G0X3HBA","jetson-customize-pcie",null,"Per-controller PCIe enable \u002F disable \u002F lanes \u002F link-speed for a Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay. Do NOT use for UPHY lane allocation or endpoint-mode bring-up.","pattanation\u002FNorvik","pattanation","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F235419268?v=4","01M71M5THHYYB15ME8R2E4FCZG","Patta","01M71M5TJM1NDM992M8PDKYR2K",0,"Apache-2.0","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002FSKILL.md",[],[19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38],"customize","jetson customize pcie","via","kernel","phase","overlay","custom","thor","for","mode","bring","lane","io","speed","do","up","use","team","controller","Meta","2026-11-10 10:56:23",false,"---\nname: jetson-customize-pcie\ndescription: >-\n  Per-controller PCIe enable \u002F disable \u002F lanes \u002F link-speed for a\n  Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay.\n  Do NOT use for UPHY lane allocation or endpoint-mode bring-up.\nversion: 0.0.1\nlicense: \"Apache-2.0\"\nmetadata:\n  data-classification: public\n  author: \"Jetson Team\"\n  tags:\n    - bsp\n    - phase-2\n    - io\n    - pcie\n  domain: meta\n---\n\n# Customize PCIe (per-controller status \u002F lanes \u002F speed)\n\n## Overview\n\nPCIe on Tegra264 (Thor, `pcie@C0..C5`) and Tegra234 (Orin,\n`pcie@C0..C10`) is split across multiple controllers that share the\nUPHY lane pool with USB3 \u002F MGBE \u002F UFS. Each controller's runtime\nbehavior is determined by **two surfaces, both required**:\n\n| Surface | Target | Authoritative for |\n|---|---|---|\n| ODMDATA `pcie@N_status=…` (+ `pcie@N_max-link-speed`, `pcie@N_pcie-mode`, `pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`) | `\u002Fpcie\u002Fpcie@N` in BPMP DTB | UPHY lane power, refclk gating, controller-side power rails |\n| Kernel-DT overlay on `&pcieN` | `\u002Fbus@0\u002Fpcie@\u003Caddr>` in kernel DTB | Kernel probe, lane width, link speed, RC\u002FEP mode |\n\nSkipping the kernel overlay on a disable lets the kernel probe a\npowered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token\non a disable leaves BPMP holding the PHY hot.\n\n**Agentic, not table-driven** — no controller table, no\n`questions.json`. Every controller, lane width, schematic-routed\nreceptacle, and authoritative DT node address is discovered at runtime\nfrom the docs + DTB + carrier pinmap.\n\nThe output is a **kernel-DT overlay commit only**. Per-controller\n`fragment@N` blocks are appended to the composite custom overlay\n`.dts` per\n[`..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md)\nand committed to the `bsp_sources\u002F` hardware repo.\n`\u002Fjetson-build-source` compiles the composite to `.dtbo` and owns its\nMakefile + flash-conf registration.\n\n**This skill MUST NOT edit `ODMDATA=\"...\"`.** All ODMDATA tokens\n(`pcie@N_status=…`, `pcie@N_max-link-speed`, `pcie@N_pcie-mode`,\n`pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`, plus the\n`uphyX-config-N` surface tokens and `UPHY_CONFIG=\"\"` clear) are\nemitted by `\u002Fjetson-customize-uphy` in a single atomic commit on the\ncarrier flash-conf fork. The allocation table this skill consumes\nfrom the UPHY sidecar already tells the operator which controllers\nare `okay` \u002F `disabled` \u002F per-lane sized; this skill only translates\nthat table into kernel-DT overlay fragments and verifies that the\noverlay agrees with the ODMDATA already committed by `customize-uphy`\n(consistency check in Step 8 — disagreement is reported, not silently\nfixed).\n\n## When to invoke\n\n- The user says \"configure PCIe\", \"enable PCIe controller\", \"set PCIe\n  num-lanes\", \"change PCIe link speed\", or asks to flip a\n  `pcie@N_status` token.\n- A specific PCIe slot or M.2 receptacle doesn't enumerate after\n  flash, OR the link trains at the wrong width \u002F speed.\n- `jetson-customize-uphy` ran and re-allocated lanes across PCIe controllers\n  (e.g. switched from `uphy0-config-7` to `uphy0-config-6` enabling\n  PCIe C3); the per-controller side now needs to be brought up.\n- `jetson-customize-mgbe` reports the QSFP path is wired but the kernel\n  doesn't probe its PCIe-side companion (rare; XFI configurations).\n\n**Prerequisites:**\n\n- Active profile with `reference_devkit:` + `custom_carrier:` blocks.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` exists\n  (`\u002Fjetson-init-source`).\n- `\u002Fjetson-derive-carrier` has run — carrier flash-conf fork is in\n  the overlay tracker.\n- `\u002Fjetson-customize-uphy` has run — its JSON sidecar at\n  `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-uphy.json`\n  drives the per-controller `enable` decision.\n- Source-of-truth docs registered or supplied at prompt: Adaptation\n  Guide, Module Design Guide, SoC TRM.\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** Refuse the run\n  if either is missing — routing on a custom carrier cannot be guessed.\n  Reference-devkit-only profiles skip this check.\n- `dtc` on PATH.\n\n## Procedure (summary)\n\nFull step-by-step walkthrough lives in\n[`references\u002Fprocedure.md`](references\u002Fprocedure.md). High-level flow:\n\n1. Resolve active target + open source-of-truth documents (incl.\n   `\u003Ccarrier-pinmap>`, `\u003Cref-dtb>`, `\u003Cuphy-state>`). Refuse if\n   `\u003Cuphy-state>` is missing.\n2. Diff PCIe topology — devkit vs custom carrier — by decompiling\n   `\u003Cref-dtb>` and grepping the schematic for `PEX\u003CN>_*` net labels.\n3. `AskUserQuestion` (multiSelect) — which controllers to customize.\n4. Per-controller verification: pinmap + schematic + `pin_verifier.py`\n   for `PE\u003CN>_CLKREQ_L`, `PE\u003CN>_RST_L`, optional `PE\u003CN>_WAKE_L`.\n5. Auto-derive per-controller plan (`enable` from `\u003Cuphy-state>`,\n   `lanes` \u002F `speed` from Adaptation Guide, `mode` hard-pinned to\n   `\"rc\"`) → mandatory confirm-or-customize gate.\n6. Append per-controller `fragment@N` blocks (marker\n   `\u002F* custom-bsp: pcie:pcie@\u003Caddr> *\u002F`) to the composite custom\n   overlay `.dts` in `bsp_sources\u002F`. Pre-flight `dtc` + `fdtoverlay`.\n   Commit via the workflow's preview gate.\n   **Do not edit `ODMDATA`** — `\u002Fjetson-customize-uphy` already emitted\n   `pcie@N_status=…`, `pcie@N_max-link-speed`, `pcie@N_pcie-mode`,\n   `pcie@N_clk-scheme`, and `pcie-cN-endpoint-enable` in its single\n   atomic ODMDATA commit. This skill only translates the per-controller\n   plan into kernel-DT overlay fragments.\n7. (Step folded into Step 6 — overlay-only emission.)\n8. Cross-check ODMDATA vs overlay consistency. On a contradictory\n   row, **stop and ask the user how to recover the two commits.\n   Never run `git reset --hard` autonomously.**\n9. Write run-state JSON sidecar at\n   `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-pcie.json`\n   + summary, then drive the downstream next-step chain via sequential\n   `AskUserQuestion` prompts per `references\u002Fprocedure.md` Step 9.\n   Never substitute a printed \"Next step: …\" line for the prompts.\n\n## Limitations\n\n- **Mode hard-pinned to RC.** Endpoint mode is only emitted when the\n  operator passes `mode_override=\"ep\"` in Step 5c.\n- **`enable` is derived, not asked.** UPHY-allocated controllers are\n  mandatorily `okay`; non-allocated are mandatorily `disabled`.\n- **No upstream BSP edits.** Output lands in `Linux_for_Tegra\u002F` +\n  `bsp_sources\u002F` only.\n- **Pre-flight overlay merge is a sanity check**, not the production\n  build. `\u002Fjetson-build-source` is authoritative.\n- **Flash-conf overlay registration is out of scope.** Owned by\n  `\u002Fjetson-build-source` Step 5.0a.\n\n## Troubleshooting\n\n- **`\u003Cuphy-state>` missing** → run `\u002Fjetson-customize-uphy` first.\n- **Slot doesn't enumerate after flash** → check `dmesg | grep pcie`;\n  re-verify ODMDATA `pcie@\u003CN>_status=okay` and the overlay fragment\n  agree (Step 8 table in\n  [`references\u002Fprocedure.md`](references\u002Fprocedure.md)).\n- **Link trains at wrong width** → confirm UPHY config in\n  `\u003Cuphy-state>` allocates the expected lane count; the kernel\n  fragment's `num-lanes` must match.\n- **`compatible` mismatch** → fix the composite root, not the\n  fragment. UEFI plugin-manager silently skips on mismatch.\n- **Contradictory ODMDATA-vs-overlay row** → ask the user; do not\n  auto-`git reset --hard`. See gotchas.\n- **Common pitfalls** — see\n  [`references\u002Fgotchas.md`](references\u002Fgotchas.md) (RC pinning, node-\n  address sourcing, stock-disabled controllers, intra-file handoff\n  with `jetson-customize-uphy`).\n\n## References\n\n- [`references\u002Fprocedure.md`](references\u002Fprocedure.md) — full nine-\n  step procedure (topology diff, plan derivation, overlay append,\n  ODMDATA cross-check, sidecar).\n- [`references\u002Fgotchas.md`](references\u002Fgotchas.md) — failure modes\n  + invariants (RC pinning, address sourcing, BPMP handoff).\n- [`..\u002F..\u002Fscripts\u002Fpin_verifier.py`](..\u002F..\u002Fscripts\u002Fpin_verifier.py)\n  — shared HSIO pin verifier (Step 4).\n- [`..\u002F..\u002Freferences\u002Fplatform_template.yaml`](..\u002F..\u002Freferences\u002Fplatform_template.yaml)\n  — `documents:` block consumed by Step 1.\n- [`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md`](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants)\n  — overlay edit protocol + commit message preview gate.\n- [`..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md)\n  — composite overlay filename \u002F skeleton \u002F append protocol.\n- [`..\u002Fjetson-customize-uphy\u002FSKILL.md`](..\u002Fjetson-customize-uphy\u002FSKILL.md)\n  — sibling skill that owns UPHY lane allocation; its sidecar drives\n  the per-controller `enable` decision.\n- [`..\u002Fjetson-customize-pinmux\u002FSKILL.md`](..\u002Fjetson-customize-pinmux\u002FSKILL.md)\n  — sibling skill invoked by Step 4 (with operator confirmation) to\n  fix HSIO pin SFIO mismatches.\n- [`..\u002Fjetson-customize-mgbe\u002FSKILL.md`](..\u002Fjetson-customize-mgbe\u002FSKILL.md)\n  — sibling for MGBE controllers; shares the two-surface (ODMDATA\n  + overlay) pattern.\n- [`..\u002Fjetson-derive-carrier\u002FSKILL.md`](..\u002Fjetson-derive-carrier\u002FSKILL.md)\n  — must run first; produces the carrier flash-conf fork edited in\n  Step 6.\n- [`..\u002Fjetson-init-source\u002FSKILL.md`](..\u002Fjetson-init-source\u002FSKILL.md)\n  — produces the overlay tracker + bsp_sources repo this skill\n  commits into.\n","# Customize PCIe (per-controller status \u002F lanes \u002F speed)\n\n## Overview\n\nPCIe on Tegra264 (Thor, `pcie@C0..C5`) and Tegra234 (Orin,\n`pcie@C0..C10`) is split across multiple controllers that share the\nUPHY lane pool with USB3 \u002F MGBE \u002F UFS. Each controller's runtime\nbehavior is determined by **two surfaces, both required**:\n\n| Surface | Target | Authoritative for |\n|---|---|---|\n| ODMDATA `pcie@N_status=…` (+ `pcie@N_max-link-speed`, `pcie@N_pcie-mode`, `pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`) | `\u002Fpcie\u002Fpcie@N` in BPMP DTB | UPHY lane power, refclk gating, controller-side power rails |\n| Kernel-DT overlay on `&pcieN` | `\u002Fbus@0\u002Fpcie@\u003Caddr>` in kernel DTB | Kernel probe, lane width, link speed, RC\u002FEP mode |\n\nSkipping the kernel overlay on a disable lets the kernel probe a\npowered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token\non a disable leaves BPMP holding the PHY hot.\n\n**Agentic, not table-driven** — no controller table, no\n`questions.json`. Every controller, lane width, schematic-routed\nreceptacle, and authoritative DT node address is discovered at runtime\nfrom the docs + DTB + carrier pinmap.\n\nThe output is a **kernel-DT overlay commit only**. Per-controller\n`fragment@N` blocks are appended to the composite custom overlay\n`.dts` per\n[`..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md)\nand committed to the `bsp_sources\u002F` hardware repo.\n`\u002Fjetson-build-source` compiles the composite to `.dtbo` and owns its\nMakefile + flash-conf registration.\n\n**This skill MUST NOT edit `ODMDATA=\"...\"`.** All ODMDATA tokens\n(`pcie@N_status=…`, `pcie@N_max-link-speed`, `pcie@N_pcie-mode`,\n`pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`, plus the\n`uphyX-config-N` surface tokens and `UPHY_CONFIG=\"\"` clear) are\nemitted by `\u002Fjetson-customize-uphy` in a single atomic commit on the\ncarrier flash-conf fork. The allocation table this skill consumes\nfrom the UPHY sidecar already tells the operator which controllers\nare `okay` \u002F `disabled` \u002F per-lane sized; this skill only translates\nthat table into kernel-DT overlay fragments and verifies that the\noverlay agrees with the ODMDATA already committed by `customize-uphy`\n(consistency check in Step 8 — disagreement is reported, not silently\nfixed).\n\n## When to invoke\n\n- The user says \"configure PCIe\", \"enable PCIe controller\", \"set PCIe\n  num-lanes\", \"change PCIe link speed\", or asks to flip a\n  `pcie@N_status` token.\n- A specific PCIe slot or M.2 receptacle doesn't enumerate after\n  flash, OR the link trains at the wrong width \u002F speed.\n- `jetson-customize-uphy` ran and re-allocated lanes across PCIe controllers\n  (e.g. switched from `uphy0-config-7` to `uphy0-config-6` enabling\n  PCIe C3); the per-controller side now needs to be brought up.\n- `jetson-customize-mgbe` reports the QSFP path is wired but the kernel\n  doesn't probe its PCIe-side companion (rare; XFI configurations).\n\n**Prerequisites:**\n\n- Active profile with `reference_devkit:` + `custom_carrier:` blocks.\n- `\u003Csource.root_path>\u002FLinux_for_Tegra\u002F.git` exists\n  (`\u002Fjetson-init-source`).\n- `\u002Fjetson-derive-carrier` has run — carrier flash-conf fork is in\n  the overlay tracker.\n- `\u002Fjetson-customize-uphy` has run — its JSON sidecar at\n  `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-uphy.json`\n  drives the per-controller `enable` decision.\n- Source-of-truth docs registered or supplied at prompt: Adaptation\n  Guide, Module Design Guide, SoC TRM.\n- **When `custom_carrier:` is present, both\n  `documents.custom_carrier_schematic` AND\n  `documents.custom_carrier_pinmux_xls` are REQUIRED.** Refuse the run\n  if either is missing — routing on a custom carrier cannot be guessed.\n  Reference-devkit-only profiles skip this check.\n- `dtc` on PATH.\n\n## Procedure (summary)\n\nFull step-by-step walkthrough lives in\n[`references\u002Fprocedure.md`](references\u002Fprocedure.md). High-level flow:\n\n1. Resolve active target + open source-of-truth documents (incl.\n   `\u003Ccarrier-pinmap>`, `\u003Cref-dtb>`, `\u003Cuphy-state>`). Refuse if\n   `\u003Cuphy-state>` is missing.\n2. Diff PCIe topology — devkit vs custom carrier — by decompiling\n   `\u003Cref-dtb>` and grepping the schematic for `PEX\u003CN>_*` net labels.\n3. `AskUserQuestion` (multiSelect) — which controllers to customize.\n4. Per-controller verification: pinmap + schematic + `pin_verifier.py`\n   for `PE\u003CN>_CLKREQ_L`, `PE\u003CN>_RST_L`, optional `PE\u003CN>_WAKE_L`.\n5. Auto-derive per-controller plan (`enable` from `\u003Cuphy-state>`,\n   `lanes` \u002F `speed` from Adaptation Guide, `mode` hard-pinned to\n   `\"rc\"`) → mandatory confirm-or-customize gate.\n6. Append per-controller `fragment@N` blocks (marker\n   `\u002F* custom-bsp: pcie:pcie@\u003Caddr> *\u002F`) to the composite custom\n   overlay `.dts` in `bsp_sources\u002F`. Pre-flight `dtc` + `fdtoverlay`.\n   Commit via the workflow's preview gate.\n   **Do not edit `ODMDATA`** — `\u002Fjetson-customize-uphy` already emitted\n   `pcie@N_status=…`, `pcie@N_max-link-speed`, `pcie@N_pcie-mode`,\n   `pcie@N_clk-scheme`, and `pcie-cN-endpoint-enable` in its single\n   atomic ODMDATA commit. This skill only translates the per-controller\n   plan into kernel-DT overlay fragments.\n7. (Step folded into Step 6 — overlay-only emission.)\n8. Cross-check ODMDATA vs overlay consistency. On a contradictory\n   row, **stop and ask the user how to recover the two commits.\n   Never run `git reset --hard` autonomously.**\n9. Write run-state JSON sidecar at\n   `\u003Cworkspace>\u002Ftarget-platform\u002F\u003Cprofile-stem>.jetson-customize-pcie.json`\n   + summary, then drive the downstream next-step chain via sequential\n   `AskUserQuestion` prompts per `references\u002Fprocedure.md` Step 9.\n   Never substitute a printed \"Next step: …\" line for the prompts.\n\n## Limitations\n\n- **Mode hard-pinned to RC.** Endpoint mode is only emitted when the\n  operator passes `mode_override=\"ep\"` in Step 5c.\n- **`enable` is derived, not asked.** UPHY-allocated controllers are\n  mandatorily `okay`; non-allocated are mandatorily `disabled`.\n- **No upstream BSP edits.** Output lands in `Linux_for_Tegra\u002F` +\n  `bsp_sources\u002F` only.\n- **Pre-flight overlay merge is a sanity check**, not the production\n  build. `\u002Fjetson-build-source` is authoritative.\n- **Flash-conf overlay registration is out of scope.** Owned by\n  `\u002Fjetson-build-source` Step 5.0a.\n\n## Troubleshooting\n\n- **`\u003Cuphy-state>` missing** → run `\u002Fjetson-customize-uphy` first.\n- **Slot doesn't enumerate after flash** → check `dmesg | grep pcie`;\n  re-verify ODMDATA `pcie@\u003CN>_status=okay` and the overlay fragment\n  agree (Step 8 table in\n  [`references\u002Fprocedure.md`](references\u002Fprocedure.md)).\n- **Link trains at wrong width** → confirm UPHY config in\n  `\u003Cuphy-state>` allocates the expected lane count; the kernel\n  fragment's `num-lanes` must match.\n- **`compatible` mismatch** → fix the composite root, not the\n  fragment. UEFI plugin-manager silently skips on mismatch.\n- **Contradictory ODMDATA-vs-overlay row** → ask the user; do not\n  auto-`git reset --hard`. See gotchas.\n- **Common pitfalls** — see\n  [`references\u002Fgotchas.md`](references\u002Fgotchas.md) (RC pinning, node-\n  address sourcing, stock-disabled controllers, intra-file handoff\n  with `jetson-customize-uphy`).\n\n## References\n\n- [`references\u002Fprocedure.md`](references\u002Fprocedure.md) — full nine-\n  step procedure (topology diff, plan derivation, overlay append,\n  ODMDATA cross-check, sidecar).\n- [`references\u002Fgotchas.md`](references\u002Fgotchas.md) — failure modes\n  + invariants (RC pinning, address sourcing, BPMP handoff).\n- [`..\u002F..\u002Fscripts\u002Fpin_verifier.py`](..\u002F..\u002Fscripts\u002Fpin_verifier.py)\n  — shared HSIO pin verifier (Step 4).\n- [`..\u002F..\u002Freferences\u002Fplatform_template.yaml`](..\u002F..\u002Freferences\u002Fplatform_template.yaml)\n  — `documents:` block consumed by Step 1.\n- [`..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md`](..\u002F..\u002Fcontext\u002Fbsp-customization-workflow.md#workflow-invariants)\n  — overlay edit protocol + commit message preview gate.\n- [`..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md`](..\u002F..\u002Freferences\u002Fbsp-customization-kernel-dtb.md)\n  — composite overlay filename \u002F skeleton \u002F append protocol.\n- [`..\u002Fjetson-customize-uphy\u002FSKILL.md`](..\u002Fjetson-customize-uphy\u002FSKILL.md)\n  — sibling skill that owns UPHY lane allocation; its sidecar drives\n  the per-controller `enable` decision.\n- [`..\u002Fjetson-customize-pinmux\u002FSKILL.md`](..\u002Fjetson-customize-pinmux\u002FSKILL.md)\n  — sibling skill invoked by Step 4 (with operator confirmation) to\n  fix HSIO pin SFIO mismatches.\n- [`..\u002Fjetson-customize-mgbe\u002FSKILL.md`](..\u002Fjetson-customize-mgbe\u002FSKILL.md)\n  — sibling for MGBE controllers; shares the two-surface (ODMDATA\n  + overlay) pattern.\n- [`..\u002Fjetson-derive-carrier\u002FSKILL.md`](..\u002Fjetson-derive-carrier\u002FSKILL.md)\n  — must run first; produces the carrier flash-conf fork edited in\n  Step 6.\n- [`..\u002Fjetson-init-source\u002FSKILL.md`](..\u002Fjetson-init-source\u002FSKILL.md)\n  — produces the overlay tracker + bsp_sources repo this skill\n  commits into.\n",{"name":5,"license":15,"version":44,"metadata":45,"description":7},"0.0.1",{"tags":46,"author":50,"domain":51,"data-classification":52},[47,48,31,49],"bsp","phase-2","pcie","Jetson Team","meta","public","claude\u002Finstall-gsd-build-foQdV","d86cd127f527124b5fd0fd0bc679a4d79b7d01d7",".agents\u002Fskills\u002Fjetson-customize-pcie","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik","https:\u002F\u002Fnorvik-orpin.vercel.app","https:\u002F\u002Fgithub.com\u002Fpattanation","2026-07-17 11:17:04",{"source":8,"skillName":5,"commands":61,"prompt":71,"zipAvailable":72},[62,65,68],{"tool":63,"command":64},"npx","npx skills add pattanation\u002FNorvik --skill jetson-customize-pcie",{"tool":66,"command":67},"bunx","bunx skills add pattanation\u002FNorvik --skill jetson-customize-pcie",{"tool":69,"command":70},"pnpm","pnpm dlx skills add pattanation\u002FNorvik --skill jetson-customize-pcie","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002FSKILL.md",true,[74,80,84,88,92,96],{"path":75,"resourceType":76,"resourceTypeDesc":77,"sizeBytes":78,"sourceHtmlUrl":79},"BENCHMARK.md","REFERENCE","参考文档",3832,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002FBENCHMARK.md",{"path":81,"resourceType":76,"resourceTypeDesc":77,"sizeBytes":82,"sourceHtmlUrl":83},"evals\u002Fevals.json",7057,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002Fevals\u002Fevals.json",{"path":85,"resourceType":76,"resourceTypeDesc":77,"sizeBytes":86,"sourceHtmlUrl":87},"references\u002Fgotchas.md",2349,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002Freferences\u002Fgotchas.md",{"path":89,"resourceType":76,"resourceTypeDesc":77,"sizeBytes":90,"sourceHtmlUrl":91},"references\u002Fprocedure.md",15200,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002Freferences\u002Fprocedure.md",{"path":93,"resourceType":76,"resourceTypeDesc":77,"sizeBytes":94,"sourceHtmlUrl":95},"skill-card.md",3760,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002Fskill-card.md",{"path":97,"resourceType":98,"resourceTypeDesc":99,"sizeBytes":100,"sourceHtmlUrl":101},"skill.oms.sig","OTHER","其他",5061,"https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fjetson-customize-pcie\u002Fskill.oms.sig",[103,136,161,185,207,222],{"skillNo":104,"name":105,"nameZh":6,"description":106,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":107,"sourceHtmlUrl":108,"categories":109,"keywords":118,"publishedAt":135},"01M71QDV4DM8T19HEHWATEF1K4","webapp-testing","Toolkit for interacting with and testing local web applications using Playwright. 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Covers Vitest, Vue Test Utils, component testing, mocking, testing patterns, and Playwright for E2E testing.","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fvue-testing-best-practices\u002FLICENSE.md","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fvue-testing-best-practices\u002FSKILL.md",[192,193],{"categoryNo":111,"categoryName":112,"taxonomyType":113,"taxonomyTypeDesc":114},{"categoryNo":116,"categoryName":117,"taxonomyType":113,"taxonomyTypeDesc":114},[195,120,196,182,197,130,198,199,200,177,201,27,202,203,204,35,205,183,206],"vue testing best practices","testing best practices","best practices","test","testing patterns","component","vitest","mocking","e2e","utils","patterns","e2e testing",{"skillNo":208,"name":209,"nameZh":6,"description":210,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":165,"licenseFileUrl":211,"sourceHtmlUrl":212,"categories":213,"keywords":215,"publishedAt":135},"01M71QD358H2DJ9THJRBP77T3T","vue-router-best-practices","Vue Router 4 patterns, navigation guards, route params, and route-component lifecycle interactions.","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fvue-router-best-practices\u002FLICENSE.md","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fvue-router-best-practices\u002FSKILL.md",[214],{"categoryNo":116,"categoryName":117,"taxonomyType":113,"taxonomyTypeDesc":114},[216,182,217,197,218,200,219,177,205,220,221],"router","vue router best practices","route","guards","navigation","lifecycle",{"skillNo":223,"name":224,"nameZh":6,"description":225,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":165,"licenseFileUrl":226,"sourceHtmlUrl":227,"categories":228,"keywords":230,"publishedAt":135},"01M71QCYPNWDE2MQZ1TF3ED5S4","vue-best-practices","MUST be used for Vue.js tasks. Strongly recommends Composition API with `\u003Cscript setup>` and TypeScript as the standard approach. Covers Vue 3, SSR, Volar, vue-tsc. Load for any Vue, .vue files, Vue Router, Pinia, or Vite with Vue work. ALWAYS use Composition API unless the project explicitly requires Options API.","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fvue-best-practices\u002FLICENSE.md","https:\u002F\u002Fgithub.com\u002Fpattanation\u002FNorvik\u002Fblob\u002Fclaude\u002Finstall-gsd-build-foQdV\u002F.agents\u002Fskills\u002Fvue-best-practices\u002FSKILL.md",[229],{"categoryNo":116,"categoryName":117,"taxonomyType":113,"taxonomyTypeDesc":114},[231,182,197,232,174,233,234,235,216,236,237,238,239,240,241,27,242,35,243,244],"vue best practices","Composition","files","tasks","api","pinia","work","options","ssr","typescript","as","vite","load","standard"]