[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M71FV8B4JB3CJPJ8RFH7RCWP":3,"skill-same:01M71FV8B4JB3CJPJ8RFH7RCWP":68},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":18,"publishedAt":31,"linkOnly":32,"markdownContent":33,"markdownBody":34,"frontMatter":35,"refName":36,"commitSha":37,"skillDirectory":38,"forksCount":14,"repositoryHtmlUrl":39,"repositoryHomepageUrl":6,"ownerHtmlUrl":40,"ownerBlogUrl":41,"ownerDescription":42,"updatedAt":43,"install":44,"resources":57},"01M71FV8B4JB3CJPJ8RFH7RCWP","review-systemverilog",null,"ALWAYS invoke this skill when reviewing SystemVerilog or Verilog code for idiomatic style, synthesizability, or best practices. NEVER review SystemVerilog or Verilog without this skill.","outcomeeng\u002Fplugins","outcomeeng","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F257335685?v=4","01M71FRVRF36XYR3HRSCGFHK2R","Outcome Engineering","01M71FRVS4BZG17DWANFJ7EPNY",1,"MIT","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Fhdl\u002Fskills\u002Freview-systemverilog\u002FSKILL.md",[],[19,20,21,22,23,24,25,26,27,28,29,30],"review systemverilog","systemverilog","review","idiomatic","never","invoke","style","when","for","best practices","Verilog","code","2026-11-10 10:12:30",false,"---\nname: review-systemverilog\ndescription: >-\n  ALWAYS invoke this skill when reviewing SystemVerilog or Verilog code for idiomatic style,\n  synthesizability, or best practices. NEVER review SystemVerilog or Verilog without this skill.\n---\n\n\u003Cobjective>\nPrioritized SystemVerilog (IEEE 1800-2017) review findings covering type discipline, always-block usage, naming conventions, and synthesizability, with legacy Verilog-2001 patterns flagged as style.\n\n\u003C\u002Fobjective>\n\n\u003Cquick_start>\nInvoke: `\u002Freview-systemverilog`\n\nProvide the SystemVerilog files to review (design files, packages, interfaces, testbenches, or any combination). The skill walks through a structured review:\n\n1. **Type & Package Review** - `logic` usage, enums, structs, packages, parameterization\n2. **Always-Block & FSM Review** - `always_ff`\u002F`always_comb`, blocking vs non-blocking, FSM patterns\n3. **Structural & Style Review** - Port declarations, instantiation, naming conventions\n4. **Synthesizability Review** - Latch detection, width mismatches, tool compatibility\n5. **Findings Report** - Prioritized improvements with idiomatic alternatives\n\n\u003C\u002Fquick_start>\n\n\u003Cessential_principles>\n\n**logic everywhere.** `wire` and `reg` are legacy. `logic` is the unified type — it works in all contexts. Only use `wire` for multi-driver nets (tri-state buses).\n\n**always_ff and always_comb, never always @.** `always_ff` enforces sequential semantics. `always_comb` enforces combinational semantics and auto-infers the sensitivity list. `always @(posedge clk)` and `always @(*)` are legacy Verilog-2001.\n\n**unique case, not bare case.** `unique case` tells the synthesizer all cases are covered and mutually exclusive. `priority case` when first-match priority encoding is intended. Bare `case` communicates nothing about designer intent.\n\n**Non-blocking (\u003C=) in always_ff, blocking (=) in always_comb.** Mixing them up causes simulation\u002Fsynthesis mismatch. `always_ff` enforces this; `always @(posedge clk)` does not.\n\n**ANSI-style ports, named connections.** Module ports declared in the header, not in a separate body. Instantiations use `.port_name(signal)`, never positional.\n\n**Packages for shared types.** Enums, structs, typedefs, constants, and functions belong in packages. No `` `define `` macros for things that can be `parameter` or `localparam`.\n\n\u003C\u002Fessential_principles>\n\n\u003Cintake>\nWhat would you like reviewed?\n\nProvide any combination of:\n\n- **Design files** (.sv, .v) - Modules, always blocks, instantiations\n- **Package files** (.sv) - Type definitions, constants, functions\n- **Interface files** (.sv) - Interface and modport definitions\n- **Testbench files** (.sv) - Stimulus, assertions, coverage\n- **Constraint files** (.xdc, .sdc) - Timing and placement constraints (for context)\n\nYou can provide file paths, paste code, or point to a directory.\n\n**Wait for the user to provide files before proceeding.**\n\n\u003C\u002Fintake>\n\n\u003Crouting>\nAfter the user provides files, execute the review workflow:\n\nRead `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` first, then follow `${CLAUDE_SKILL_DIR}\u002Fworkflows\u002Fsystemverilog-review.md` exactly.\n\n| User Provides   | Reference to Read                                        | Additional Context                       |\n| --------------- | -------------------------------------------------------- | ---------------------------------------- |\n| Design files    | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Full review against all idiom categories |\n| Package files   | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Focus on type discipline, naming         |\n| Interface files | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Focus on modport, parameterization       |\n| Testbench files | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Testbench-specific idioms apply          |\n| Mixed           | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Review each file in its appropriate mode |\n\n\u003C\u002Frouting>\n\n\u003Creference_index>\n\n| File                                                     | Purpose                                                        |\n| -------------------------------------------------------- | -------------------------------------------------------------- |\n| `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Comprehensive idiomatic SystemVerilog IEEE 1800-2017 reference |\n| `${CLAUDE_SKILL_DIR}\u002Fworkflows\u002Fsystemverilog-review.md`  | Step-by-step review procedure with finding format              |\n\n\u003C\u002Freference_index>\n\n\u003Csuccess_criteria>\nReview is complete when:\n\n- [ ] Every file reviewed against idiomatic SystemVerilog standards\n- [ ] Findings are specific: file, line, what, why, idiomatic alternative\n- [ ] Findings are prioritized: P0 (incorrect hardware), P1 (quality\u002Fmaintainability), P2 (style)\n- [ ] Legacy Verilog-2001 patterns flagged\n- [ ] Latch and blocking\u002Fnon-blocking issues identified\n- [ ] Naming convention deviations noted\n- [ ] Summary table of all findings delivered\n\n\u003C\u002Fsuccess_criteria>\n","\u003Cobjective>\nPrioritized SystemVerilog (IEEE 1800-2017) review findings covering type discipline, always-block usage, naming conventions, and synthesizability, with legacy Verilog-2001 patterns flagged as style.\n\n\u003C\u002Fobjective>\n\n\u003Cquick_start>\nInvoke: `\u002Freview-systemverilog`\n\nProvide the SystemVerilog files to review (design files, packages, interfaces, testbenches, or any combination). The skill walks through a structured review:\n\n1. **Type & Package Review** - `logic` usage, enums, structs, packages, parameterization\n2. **Always-Block & FSM Review** - `always_ff`\u002F`always_comb`, blocking vs non-blocking, FSM patterns\n3. **Structural & Style Review** - Port declarations, instantiation, naming conventions\n4. **Synthesizability Review** - Latch detection, width mismatches, tool compatibility\n5. **Findings Report** - Prioritized improvements with idiomatic alternatives\n\n\u003C\u002Fquick_start>\n\n\u003Cessential_principles>\n\n**logic everywhere.** `wire` and `reg` are legacy. `logic` is the unified type — it works in all contexts. Only use `wire` for multi-driver nets (tri-state buses).\n\n**always_ff and always_comb, never always @.** `always_ff` enforces sequential semantics. `always_comb` enforces combinational semantics and auto-infers the sensitivity list. `always @(posedge clk)` and `always @(*)` are legacy Verilog-2001.\n\n**unique case, not bare case.** `unique case` tells the synthesizer all cases are covered and mutually exclusive. `priority case` when first-match priority encoding is intended. Bare `case` communicates nothing about designer intent.\n\n**Non-blocking (\u003C=) in always_ff, blocking (=) in always_comb.** Mixing them up causes simulation\u002Fsynthesis mismatch. `always_ff` enforces this; `always @(posedge clk)` does not.\n\n**ANSI-style ports, named connections.** Module ports declared in the header, not in a separate body. Instantiations use `.port_name(signal)`, never positional.\n\n**Packages for shared types.** Enums, structs, typedefs, constants, and functions belong in packages. No `` `define `` macros for things that can be `parameter` or `localparam`.\n\n\u003C\u002Fessential_principles>\n\n\u003Cintake>\nWhat would you like reviewed?\n\nProvide any combination of:\n\n- **Design files** (.sv, .v) - Modules, always blocks, instantiations\n- **Package files** (.sv) - Type definitions, constants, functions\n- **Interface files** (.sv) - Interface and modport definitions\n- **Testbench files** (.sv) - Stimulus, assertions, coverage\n- **Constraint files** (.xdc, .sdc) - Timing and placement constraints (for context)\n\nYou can provide file paths, paste code, or point to a directory.\n\n**Wait for the user to provide files before proceeding.**\n\n\u003C\u002Fintake>\n\n\u003Crouting>\nAfter the user provides files, execute the review workflow:\n\nRead `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` first, then follow `${CLAUDE_SKILL_DIR}\u002Fworkflows\u002Fsystemverilog-review.md` exactly.\n\n| User Provides   | Reference to Read                                        | Additional Context                       |\n| --------------- | -------------------------------------------------------- | ---------------------------------------- |\n| Design files    | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Full review against all idiom categories |\n| Package files   | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Focus on type discipline, naming         |\n| Interface files | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Focus on modport, parameterization       |\n| Testbench files | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Testbench-specific idioms apply          |\n| Mixed           | `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Review each file in its appropriate mode |\n\n\u003C\u002Frouting>\n\n\u003Creference_index>\n\n| File                                                     | Purpose                                                        |\n| -------------------------------------------------------- | -------------------------------------------------------------- |\n| `${CLAUDE_SKILL_DIR}\u002Freferences\u002Fsystemverilog-idioms.md` | Comprehensive idiomatic SystemVerilog IEEE 1800-2017 reference |\n| `${CLAUDE_SKILL_DIR}\u002Fworkflows\u002Fsystemverilog-review.md`  | Step-by-step review procedure with finding format              |\n\n\u003C\u002Freference_index>\n\n\u003Csuccess_criteria>\nReview is complete when:\n\n- [ ] Every file reviewed against idiomatic SystemVerilog standards\n- [ ] Findings are specific: file, line, what, why, idiomatic alternative\n- [ ] Findings are prioritized: P0 (incorrect hardware), P1 (quality\u002Fmaintainability), P2 (style)\n- [ ] Legacy Verilog-2001 patterns flagged\n- [ ] Latch and blocking\u002Fnon-blocking issues identified\n- [ ] Naming convention deviations noted\n- [ ] Summary table of all findings delivered\n\n\u003C\u002Fsuccess_criteria>\n",{"name":5,"description":7},"main","978d51c51d68c99cffb2ba48f7cad9d2f07e5738","src\u002Fplugins\u002Fhdl\u002Fskills\u002Freview-systemverilog","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins","https:\u002F\u002Fgithub.com\u002Foutcomeeng","https:\u002F\u002Foutcome.engineering","Spec-driven development for AI-assisted engineering","2026-11-12 11:34:11",{"source":8,"skillName":5,"commands":45,"prompt":55,"zipAvailable":56},[46,49,52],{"tool":47,"command":48},"npx","npx skills add outcomeeng\u002Fplugins --skill review-systemverilog",{"tool":50,"command":51},"bunx","bunx skills add outcomeeng\u002Fplugins --skill review-systemverilog",{"tool":53,"command":54},"pnpm","pnpm dlx skills add outcomeeng\u002Fplugins --skill review-systemverilog","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Fhdl\u002Fskills\u002Freview-systemverilog\u002FSKILL.md",true,[58,64],{"path":59,"resourceType":60,"resourceTypeDesc":61,"sizeBytes":62,"sourceHtmlUrl":63},"references\u002Fsystemverilog-idioms.md","REFERENCE","参考文档",20491,"https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Fhdl\u002Fskills\u002Freview-systemverilog\u002Freferences\u002Fsystemverilog-idioms.md",{"path":65,"resourceType":60,"resourceTypeDesc":61,"sizeBytes":66,"sourceHtmlUrl":67},"workflows\u002Fsystemverilog-review.md",6811,"https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Fhdl\u002Fskills\u002Freview-systemverilog\u002Fworkflows\u002Fsystemverilog-review.md",[69,75,109,125,142,154],{"skillNo":70,"name":71,"nameZh":6,"description":6,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":72,"categories":73,"keywords":74,"publishedAt":31},"01M71G25RZTPQG9KJ00JCHC1F7","plugin","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Ftemplates\u002Fplugin\u002FSKILL.md",[],[71],{"skillNo":76,"name":77,"nameZh":6,"description":78,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":79,"categories":80,"keywords":91,"publishedAt":31},"01M71G23DCX3SV60H63HBBKQ6J","sanitize-powerpoint","ALWAYS invoke this skill when sanitizing, cleaning up, auditing, or aligning a PowerPoint (.pptx) deck — slide-master and layout structure, layout type attributes, stray fonts, non-theme colors, or layout naming. NEVER hand-edit pptx XML without this skill.","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Fwork\u002Fskills\u002Fsanitize-powerpoint\u002FSKILL.md",[81,86],{"categoryNo":82,"categoryName":83,"taxonomyType":84,"taxonomyTypeDesc":85},"01JBSEEDCAT000000000000003","演示文稿","SCENARIO","使用场景",{"categoryNo":87,"categoryName":88,"taxonomyType":89,"taxonomyTypeDesc":90},"01JBSEEDCAT000000000000034","行政与办公人员","PROFESSION","适用职业",[92,93,94,95,96,97,98,23,99,100,101,102,103,104,105,106,107,108,24,26],"sanitize powerpoint","powerpoint","sanitize","fonts","type","cleaning","structure","attributes","theme","pptx","naming","layout","deck","up","edit","xml","master",{"skillNo":110,"name":111,"nameZh":6,"description":112,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":113,"categories":114,"keywords":115,"publishedAt":31},"01M71G21PQKBCDECHGVYSKPJW5","draw-excalidraw","ALWAYS invoke this skill when creating Excalidraw diagrams, visualizing workflows, architectures, or concepts. NEVER generate Excalidraw JSON without this skill.","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Fwork\u002Fskills\u002Fdraw-excalidraw\u002FSKILL.md",[],[116,117,118,119,120,23,24,121,122,26,123,124],"draw excalidraw","excalidraw","draw","diagrams","architectures","generate","workflows","concepts","json",{"skillNo":126,"name":127,"nameZh":6,"description":128,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":129,"categories":130,"keywords":134,"publishedAt":31},"01M71G1ZMNGFD37RZYM620XM2C","typescript-test-standards","TypeScript test standards enforced across all skills. Loaded by other skills, not invoked directly.","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Ftypescript\u002Fskills\u002Ftypescript-test-standards\u002FSKILL.md",[131],{"categoryNo":132,"categoryName":133,"taxonomyType":84,"taxonomyTypeDesc":85},"01JBSEEDCAT000000000000008","测试与质量",[135,136,137,138,139,140,141],"typescript","typescript test standards","test","standards","false","read","across",{"skillNo":143,"name":144,"nameZh":6,"description":145,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":146,"categories":147,"keywords":151,"publishedAt":31},"01M71G1XBH0X1VCTR7269MDGSY","typescript-code-standards","TypeScript code standards enforced across all skills. Loaded by other skills, not invoked directly.","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Ftypescript\u002Fskills\u002Ftypescript-code-standards\u002FSKILL.md",[148],{"categoryNo":149,"categoryName":150,"taxonomyType":89,"taxonomyTypeDesc":90},"01JBSEEDCAT000000000000030","开发工程师",[135,30,152,153,138,139,140,141],"typescript code standards","code standards",{"skillNo":155,"name":156,"nameZh":6,"description":157,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":158,"categories":159,"keywords":160,"publishedAt":31},"01M71G1TQ3VN45SJ75DFMJDB9W","typescript-architecture-standards","TypeScript ADR conventions enforced across architect and auditor skills. Loaded by other skills, not invoked directly.","https:\u002F\u002Fgithub.com\u002Foutcomeeng\u002Fplugins\u002Fblob\u002Fmain\u002Fsrc\u002Fplugins\u002Ftypescript\u002Fskills\u002Ftypescript-architecture-standards\u002FSKILL.md",[],[161,138,162,163,135,164,165,141,140,166,139,167],"architecture standards","typescript architecture standards","architecture","adr","architect","auditor","conventions"]