[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"skill:01M6MDYW41K9B4GCNA2TPTYD8F":3,"skill-same:01M6MDYW41K9B4GCNA2TPTYD8F":76},{"skillNo":4,"name":5,"nameZh":6,"description":7,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":16,"categories":17,"keywords":26,"publishedAt":47,"linkOnly":48,"markdownContent":49,"markdownBody":50,"frontMatter":51,"refName":52,"commitSha":53,"skillDirectory":54,"forksCount":55,"repositoryHtmlUrl":56,"repositoryHomepageUrl":57,"ownerHtmlUrl":58,"ownerBlogUrl":59,"ownerDescription":60,"updatedAt":61,"install":62,"resources":75},"01M6MDYW41K9B4GCNA2TPTYD8F","jlcpcb",null,"JLCPCB PCB fabrication and assembly — BOM\u002FCPL generation, basic vs extended parts, assembly constraints, design rules, ordering workflow. Use with KiCad for JLCPCB manufacturing. Use this skill when the user mentions JLCPCB, wants to order PCBs or assembled boards, needs prototype bare PCBs and stencils, wants to know JLCPCB design rules and capabilities, or is asking about PCB manufacturing costs or turnaround times. For gerber\u002FCPL export, stencil ordering, and BOM management, see the `bom` skill.","hashgraph-online\u002Fawesome-codex-plugins","hashgraph-online","https:\u002F\u002Favatars.githubusercontent.com\u002Fu\u002F160371962?v=4","01M6CNB6NRJVNNGN14TR01Q6D3","HOL (Hashgraph Online)","01M6JT1HSKKG9V68KQAQGBA7XP",1566,"Apache-2.0","https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Faklofas\u002Fkicad-happy\u002Fskills\u002Fjlcpcb\u002FSKILL.md",[18,23],{"categoryNo":19,"categoryName":20,"taxonomyType":21,"taxonomyTypeDesc":22},"01JBSEEDCAT000000000000015","视觉设计","SCENARIO","使用场景",{"categoryNo":24,"categoryName":25,"taxonomyType":21,"taxonomyTypeDesc":22},"01JBSEEDCAT000000000000023","Skill与智能体开发",[5,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46],"for","fabrication","when","bare","generation","prototype","with","Rules","bom","use","basic","kicad","gerber","pcb","assembly","export","manufacturing","capabilities","workflow","design","2026-11-10 10:12:30",false,"---\nname: jlcpcb\ndescription: JLCPCB PCB fabrication and assembly — BOM\u002FCPL generation, basic vs extended parts, assembly constraints, design rules, ordering workflow. Use with KiCad for JLCPCB manufacturing. Use this skill when the user mentions JLCPCB, wants to order PCBs or assembled boards, needs prototype bare PCBs and stencils, wants to know JLCPCB design rules and capabilities, or is asking about PCB manufacturing costs or turnaround times. For gerber\u002FCPL export, stencil ordering, and BOM management, see the `bom` skill.\n---\n\n# JLCPCB — PCB Fabrication & Assembly\n\nJLCPCB is a PCB fabrication and assembly service based in Shenzhen, China. It is a sister company to LCSC Electronics (common ownership) — they share the same parts library.\n\n**Typical usage**: Order bare prototype PCBs + framed stencil from JLCPCB during prototyping (parts sourced separately from DigiKey\u002FMouser, hand-assembled in lab). For production runs (100s qty), order fully assembled boards from JLCPCB using LCSC parts. PCBWay is an alternative assembler. For component searching, see the `lcsc` skill. For BOM management, gerber\u002FCPL export, and stencil ordering, see the `bom` skill.\n\n## Related Skills\n\n| Skill | Purpose |\n|-------|---------|\n| `kicad` | Read\u002Fanalyze KiCad project files, DFM scoring against JLCPCB capabilities |\n| `bom` | BOM management, gerber\u002FCPL export, stencil ordering |\n| `digikey` | Search DigiKey (prototype sourcing, primary — also preferred for datasheet downloads via API) |\n| `mouser` | Search Mouser (prototype sourcing, secondary) |\n| `lcsc` | Search LCSC (production sourcing — JLCPCB uses LCSC parts library) |\n| `pcbway` | Alternative PCB fabrication & assembly |\n| `emc` | EMC pre-compliance risk analysis — run before fab to catch EMC issues |\n| `spice` | SPICE simulation — verify analog subcircuits before committing to fab |\n\n## Assembly Parts Library\n\n### Part Categories\n\n| Category | Description | Assembly Fee |\n|----------|-------------|--------------|\n| **Basic** | Common parts (resistors, caps, diodes, common ICs) pre-loaded on pick-and-place machines | No extra fee |\n| **Extended** | 300k+ less common parts loaded on demand | $3 per unique extended part |\n\n> JLCPCB occasionally promotes a subset of frequently-used extended parts with a discounted or waived feeder fee (the program's name and terms shift over time). Check the current JLCPCB parts library page for any specific extended part before assuming the standard $3 fee applies.\n\n### LCSC Part Numbers\n\nEvery assembly component is identified by an **LCSC Part Number** (`Cxxxxx`, e.g., `C14663`). This is the definitive identifier for BOM matching. See the `lcsc` skill for searching parts.\n\n### Parts Search (JLCPCB-Specific)\n\n- Parts library: `https:\u002F\u002Fjlcpcb.com\u002Fparts\u002FcomponentSearch?searchTxt=\u003Cquery>`\n- Basic parts only: `https:\u002F\u002Fjlcpcb.com\u002Fparts\u002Fbasic_parts`\n\n## BOM Format for Assembly\n\nJLCPCB accepts CSV, XLS, or XLSX BOMs with these columns:\n\n| Column | Required | Description |\n|--------|----------|-------------|\n| `Comment` \u002F `Value` | Yes | Component value (e.g., 100nF, 10k) |\n| `Designator` | Yes | Reference designators, comma-separated (e.g., C1,C2,C5) |\n| `Footprint` | Yes | Package\u002Ffootprint name |\n| `LCSC Part #` | Recommended | LCSC part number (Cxxxxx) — guarantees exact match |\n\nThe column header for LCSC numbers must be exactly **\"LCSC Part #\"** or **\"LCSC Part Number\"** — typos cause upload failures.\n\n### KiCad BOM Export for JLCPCB\n\n1. In KiCad schematic editor, add an `LCSC` field to each symbol with the LCSC part number\n2. Export BOM as CSV with columns: Reference, Value, Footprint, LCSC\n3. Rename columns to match JLCPCB's expected format:\n   - `Reference` -> `Designator`\n   - `Value` -> `Comment`\n   - `Footprint` -> `Footprint`\n   - `LCSC` -> `LCSC Part #`\n\nFor gerber export settings, CPL format, and stencil ordering, see the `bom` skill.\n\n## JLCPCB Official API (Approval Required)\n\nApply at `https:\u002F\u002Fapi.jlcpcb.com`. Access is gated — requires review based on order history and business profile.\n\nAvailable APIs (once approved):\n- **Components API** — real-time pricing, inventory, component specs\n- **PCB API** — upload gerbers, get quotes, place orders, track status\n- **Stencil API** — stencil quoting and ordering\n- **3D Printing API** — SLA\u002FMJF\u002FSLM\u002FFDM ordering\n\n## PCB Design Rules (JLCPCB Capabilities)\n\n### Standard PCB (1-2 layers)\n\n| Parameter | Minimum |\n|-----------|---------|\n| Trace width | 0.127mm (5mil) |\n| Trace spacing | 0.127mm (5mil) |\n| Via diameter | 0.45mm |\n| Via drill | 0.2mm |\n| Annular ring | 0.125mm |\n| Min hole size | 0.2mm |\n| Board thickness | 0.4-2.4mm (default 1.6mm) |\n| Min board size | 6x6mm |\n| Max board size | 500x400mm (2-layer) |\n\n### Multi-layer (4+ layers)\n\n| Parameter | Minimum |\n|-----------|---------|\n| Trace width | 0.09mm (3.5mil) |\n| Trace spacing | 0.09mm (3.5mil) |\n| Via diameter | 0.25mm |\n| Via drill | 0.15mm |\n| Board thickness | 0.6-2.4mm |\n\n### Importing DRU into KiCad\n\nIf you have a JLCPCB `.kicad_dru` design rules file, import it in KiCad Board Editor > Board Setup > Design Rules > Import Settings.\n\n## Assembly Constraints\n\n### Economic vs Standard Assembly\n\n| Feature | Economic | Standard |\n|---------|----------|----------|\n| Sides | Top only | Top + Bottom |\n| Component types | SMD only | SMD + through-hole |\n| Min component size | 0201 | 01005 |\n| Fine-pitch BGA\u002FQFP | Down to 0.5mm pitch | Down to 0.4mm pitch |\n| Turnaround | ~3-5 days | ~3-5 days |\n| Extended part fee | $3 per unique part | $3 per unique part |\n\n### General Constraints\n\n- **Minimum order**: 5 PCBs for assembly\n- **Unique parts limit**: No hard limit, but each extended part adds $3\n- **Basic parts**: No extra fee, pre-loaded on machines\n\n## Rotation Offsets\n\nJLCPCB's pick-and-place uses different rotation conventions than KiCad for some footprints. Common offsets:\n\n| Footprint Family | Typical Offset |\n|-----------------|----------------|\n| SOT-23, SOT-23-5, SOT-23-6 | +180° |\n| SOT-223 | +180° |\n| SOIC-8, SOIC-16 | +90° or +270° |\n| QFN (all sizes) | +90° |\n| SMA\u002FSMB\u002FSMC diodes | +180° |\n| USB-C connectors | Varies — check datasheet |\n\nTo fix rotation issues:\n1. Add rotation corrections directly in the CPL file before uploading (adjust the Rotation column)\n2. For custom footprints, verify pin 1 orientation matches JLCPCB expectations\n3. JLCPCB's review step catches major errors, but subtle 180° rotations on symmetric parts (caps, resistors) may slip through\n4. After first assembly order, note any rotation corrections needed and apply them to future CPL exports\n\n## Ordering Workflow\n\n### Prototype Order (Bare PCB + Stencil)\n\n1. **Export gerbers** from KiCad (see `bom` skill for export settings)\n2. Upload gerbers to `https:\u002F\u002Fcart.jlcpcb.com\u002Fquote` — configure layers, thickness, color, qty\n3. Add a **framed stencil** to the cart (uses paste layers from your gerbers)\n4. Order — PCBs and stencil typically arrive in ~1 week\n\n### Production Order (Assembled Boards)\n\n1. **Export gerbers** from KiCad (see `bom` skill for export settings)\n2. **Export BOM** as CSV with LCSC part numbers (format above)\n3. **Export CPL** (placement file) as CSV (see `bom` skill for format)\n4. Upload gerbers to `https:\u002F\u002Fcart.jlcpcb.com\u002Fquote` — configure layers, thickness, color, qty\n5. Enable \"PCB Assembly\", select Economic or Standard\n6. Upload BOM and CPL files\n7. Review part matching — fix any unmatched parts by searching LCSC numbers\n8. Confirm and order\n\n### Translating Altium \u002F KiCad BOM and CPL files\n\nFor boards exported from Altium (or other tools) whose BOM\u002FCPL formats\ndon't match JLCPCB's expected columns, the `bom` skill ships\n`translate_bom_pnp.py` to convert them. `\u003Cbom-skill-path>` is the installed bom skill directory. Two subcommands:\n\n```bash\n# BOM: KiCad\u002FAltium CSV → JLCPCB BOM CSV (Comment, Designator, Footprint,\n#                                         LCSC Part #, MPN, Manufacturer,\n#                                         Quantity, Notes), DNP rows left out, R1-R4 expanded.\n#                                         LCSC Part # is written empty even if the input has one:\n#                                         fill it before upload.\npython3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py bom input_bom.csv -o jlc_bom.csv\n\n# CPL: input CPL → JLCPCB Pick-and-Place CSV (Designator, Mid X, Mid Y,\n#                                              Layer, Rotation), with mil→mm\n#                                              and TopLayer\u002FBottomLayer\n#                                              normalization\npython3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py pnp input_cpl.csv -o jlc_cpl.csv --units \u003Cin|mm>\n# (--units must name the unit the file was exported in: a KiCad position CSV\n#  has no unit marker and kicad-cli exports inches unless told --units mm)\n```\n\n#### The 3-step PCBA upload workflow (avoids rejection)\n\nJLCPCB's PCBA web upload rejects orders when the CPL contains designators\nthat aren't in the BOM (mechanical holes, fiducials, test points, etc.\nthat appear in the CPL output but aren't assembly components). The\ntranslator's `--bom` filter mode solves this:\n\n1. **Translate the BOM first** — produces the JLCPCB-format BOM and\n   establishes the authoritative designator set:\n   ```bash\n   python3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py bom input_bom.csv -o jlc_bom.csv\n   ```\n\n2. **Translate the CPL with `--bom` filter** — intersects CPL designators\n   with BOM designators, dropping orphans:\n   ```bash\n   python3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py pnp input_cpl.csv -o jlc_cpl.csv --units \u003Cin|mm> --bom jlc_bom.csv\n   ```\n   The returned `filtered_orphans` count plus `filtered_orphan_samples`\n   list lets the operator confirm which CPL rows were dropped — sanity-\n   check this list before uploading. Common orphans (mounting holes,\n   fiducials, test points) are expected; anything else may indicate a\n   BOM\u002FPCB mismatch worth investigating.\n\n3. **Tabulate consigned-parts cost separately** — JLCPCB's quote does\n   not auto-itemize consigned (user-supplied) part costs. Build a quote\n   summary that shows: PCB fabrication, PCBA assembly fee, basic vs\n   extended parts cost (per JLCPCB invoice), and a separate\n   user-sourced parts subtotal. Without this breakdown the quote\n   understates true unit cost by the consigned-parts amount.\n\nThis workflow is documented because JLCPCB's web upload UX silently\nrejects orphan-designator CPLs with an unhelpful error; the parity\ncheck via `--bom` is the single highest-value step in shipping a\nclean PCBA order.\n\n## Tips\n\n- **Prefer Basic parts** — no extra fee, always in stock, faster assembly\n- **Check stock before ordering** — extended parts can go out of stock; use the `lcsc` skill to search\n- **Panel by JLCPCB** — for small boards, let JLCPCB panelize (cheaper) vs custom panels\n- **Lead-free solder** — default is leaded (HASL); select lead-free HASL or ENIG if needed\n- **Impedance control** — available for multi-layer boards, specify stackup in order notes\n- **Castellated holes** — supported, enable in order options\n- **V-cuts and mouse bites** — supported for panel separation\n- **Silkscreen minimum** — 0.8mm height, 0.15mm line width for readable text\n- **Edge clearance** — keep copper >=0.3mm from board edge (0.5mm recommended)\n","# JLCPCB — PCB Fabrication & Assembly\n\nJLCPCB is a PCB fabrication and assembly service based in Shenzhen, China. It is a sister company to LCSC Electronics (common ownership) — they share the same parts library.\n\n**Typical usage**: Order bare prototype PCBs + framed stencil from JLCPCB during prototyping (parts sourced separately from DigiKey\u002FMouser, hand-assembled in lab). For production runs (100s qty), order fully assembled boards from JLCPCB using LCSC parts. PCBWay is an alternative assembler. For component searching, see the `lcsc` skill. For BOM management, gerber\u002FCPL export, and stencil ordering, see the `bom` skill.\n\n## Related Skills\n\n| Skill | Purpose |\n|-------|---------|\n| `kicad` | Read\u002Fanalyze KiCad project files, DFM scoring against JLCPCB capabilities |\n| `bom` | BOM management, gerber\u002FCPL export, stencil ordering |\n| `digikey` | Search DigiKey (prototype sourcing, primary — also preferred for datasheet downloads via API) |\n| `mouser` | Search Mouser (prototype sourcing, secondary) |\n| `lcsc` | Search LCSC (production sourcing — JLCPCB uses LCSC parts library) |\n| `pcbway` | Alternative PCB fabrication & assembly |\n| `emc` | EMC pre-compliance risk analysis — run before fab to catch EMC issues |\n| `spice` | SPICE simulation — verify analog subcircuits before committing to fab |\n\n## Assembly Parts Library\n\n### Part Categories\n\n| Category | Description | Assembly Fee |\n|----------|-------------|--------------|\n| **Basic** | Common parts (resistors, caps, diodes, common ICs) pre-loaded on pick-and-place machines | No extra fee |\n| **Extended** | 300k+ less common parts loaded on demand | $3 per unique extended part |\n\n> JLCPCB occasionally promotes a subset of frequently-used extended parts with a discounted or waived feeder fee (the program's name and terms shift over time). Check the current JLCPCB parts library page for any specific extended part before assuming the standard $3 fee applies.\n\n### LCSC Part Numbers\n\nEvery assembly component is identified by an **LCSC Part Number** (`Cxxxxx`, e.g., `C14663`). This is the definitive identifier for BOM matching. See the `lcsc` skill for searching parts.\n\n### Parts Search (JLCPCB-Specific)\n\n- Parts library: `https:\u002F\u002Fjlcpcb.com\u002Fparts\u002FcomponentSearch?searchTxt=\u003Cquery>`\n- Basic parts only: `https:\u002F\u002Fjlcpcb.com\u002Fparts\u002Fbasic_parts`\n\n## BOM Format for Assembly\n\nJLCPCB accepts CSV, XLS, or XLSX BOMs with these columns:\n\n| Column | Required | Description |\n|--------|----------|-------------|\n| `Comment` \u002F `Value` | Yes | Component value (e.g., 100nF, 10k) |\n| `Designator` | Yes | Reference designators, comma-separated (e.g., C1,C2,C5) |\n| `Footprint` | Yes | Package\u002Ffootprint name |\n| `LCSC Part #` | Recommended | LCSC part number (Cxxxxx) — guarantees exact match |\n\nThe column header for LCSC numbers must be exactly **\"LCSC Part #\"** or **\"LCSC Part Number\"** — typos cause upload failures.\n\n### KiCad BOM Export for JLCPCB\n\n1. In KiCad schematic editor, add an `LCSC` field to each symbol with the LCSC part number\n2. Export BOM as CSV with columns: Reference, Value, Footprint, LCSC\n3. Rename columns to match JLCPCB's expected format:\n   - `Reference` -> `Designator`\n   - `Value` -> `Comment`\n   - `Footprint` -> `Footprint`\n   - `LCSC` -> `LCSC Part #`\n\nFor gerber export settings, CPL format, and stencil ordering, see the `bom` skill.\n\n## JLCPCB Official API (Approval Required)\n\nApply at `https:\u002F\u002Fapi.jlcpcb.com`. Access is gated — requires review based on order history and business profile.\n\nAvailable APIs (once approved):\n- **Components API** — real-time pricing, inventory, component specs\n- **PCB API** — upload gerbers, get quotes, place orders, track status\n- **Stencil API** — stencil quoting and ordering\n- **3D Printing API** — SLA\u002FMJF\u002FSLM\u002FFDM ordering\n\n## PCB Design Rules (JLCPCB Capabilities)\n\n### Standard PCB (1-2 layers)\n\n| Parameter | Minimum |\n|-----------|---------|\n| Trace width | 0.127mm (5mil) |\n| Trace spacing | 0.127mm (5mil) |\n| Via diameter | 0.45mm |\n| Via drill | 0.2mm |\n| Annular ring | 0.125mm |\n| Min hole size | 0.2mm |\n| Board thickness | 0.4-2.4mm (default 1.6mm) |\n| Min board size | 6x6mm |\n| Max board size | 500x400mm (2-layer) |\n\n### Multi-layer (4+ layers)\n\n| Parameter | Minimum |\n|-----------|---------|\n| Trace width | 0.09mm (3.5mil) |\n| Trace spacing | 0.09mm (3.5mil) |\n| Via diameter | 0.25mm |\n| Via drill | 0.15mm |\n| Board thickness | 0.6-2.4mm |\n\n### Importing DRU into KiCad\n\nIf you have a JLCPCB `.kicad_dru` design rules file, import it in KiCad Board Editor > Board Setup > Design Rules > Import Settings.\n\n## Assembly Constraints\n\n### Economic vs Standard Assembly\n\n| Feature | Economic | Standard |\n|---------|----------|----------|\n| Sides | Top only | Top + Bottom |\n| Component types | SMD only | SMD + through-hole |\n| Min component size | 0201 | 01005 |\n| Fine-pitch BGA\u002FQFP | Down to 0.5mm pitch | Down to 0.4mm pitch |\n| Turnaround | ~3-5 days | ~3-5 days |\n| Extended part fee | $3 per unique part | $3 per unique part |\n\n### General Constraints\n\n- **Minimum order**: 5 PCBs for assembly\n- **Unique parts limit**: No hard limit, but each extended part adds $3\n- **Basic parts**: No extra fee, pre-loaded on machines\n\n## Rotation Offsets\n\nJLCPCB's pick-and-place uses different rotation conventions than KiCad for some footprints. Common offsets:\n\n| Footprint Family | Typical Offset |\n|-----------------|----------------|\n| SOT-23, SOT-23-5, SOT-23-6 | +180° |\n| SOT-223 | +180° |\n| SOIC-8, SOIC-16 | +90° or +270° |\n| QFN (all sizes) | +90° |\n| SMA\u002FSMB\u002FSMC diodes | +180° |\n| USB-C connectors | Varies — check datasheet |\n\nTo fix rotation issues:\n1. Add rotation corrections directly in the CPL file before uploading (adjust the Rotation column)\n2. For custom footprints, verify pin 1 orientation matches JLCPCB expectations\n3. JLCPCB's review step catches major errors, but subtle 180° rotations on symmetric parts (caps, resistors) may slip through\n4. After first assembly order, note any rotation corrections needed and apply them to future CPL exports\n\n## Ordering Workflow\n\n### Prototype Order (Bare PCB + Stencil)\n\n1. **Export gerbers** from KiCad (see `bom` skill for export settings)\n2. Upload gerbers to `https:\u002F\u002Fcart.jlcpcb.com\u002Fquote` — configure layers, thickness, color, qty\n3. Add a **framed stencil** to the cart (uses paste layers from your gerbers)\n4. Order — PCBs and stencil typically arrive in ~1 week\n\n### Production Order (Assembled Boards)\n\n1. **Export gerbers** from KiCad (see `bom` skill for export settings)\n2. **Export BOM** as CSV with LCSC part numbers (format above)\n3. **Export CPL** (placement file) as CSV (see `bom` skill for format)\n4. Upload gerbers to `https:\u002F\u002Fcart.jlcpcb.com\u002Fquote` — configure layers, thickness, color, qty\n5. Enable \"PCB Assembly\", select Economic or Standard\n6. Upload BOM and CPL files\n7. Review part matching — fix any unmatched parts by searching LCSC numbers\n8. Confirm and order\n\n### Translating Altium \u002F KiCad BOM and CPL files\n\nFor boards exported from Altium (or other tools) whose BOM\u002FCPL formats\ndon't match JLCPCB's expected columns, the `bom` skill ships\n`translate_bom_pnp.py` to convert them. `\u003Cbom-skill-path>` is the installed bom skill directory. Two subcommands:\n\n```bash\n# BOM: KiCad\u002FAltium CSV → JLCPCB BOM CSV (Comment, Designator, Footprint,\n#                                         LCSC Part #, MPN, Manufacturer,\n#                                         Quantity, Notes), DNP rows left out, R1-R4 expanded.\n#                                         LCSC Part # is written empty even if the input has one:\n#                                         fill it before upload.\npython3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py bom input_bom.csv -o jlc_bom.csv\n\n# CPL: input CPL → JLCPCB Pick-and-Place CSV (Designator, Mid X, Mid Y,\n#                                              Layer, Rotation), with mil→mm\n#                                              and TopLayer\u002FBottomLayer\n#                                              normalization\npython3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py pnp input_cpl.csv -o jlc_cpl.csv --units \u003Cin|mm>\n# (--units must name the unit the file was exported in: a KiCad position CSV\n#  has no unit marker and kicad-cli exports inches unless told --units mm)\n```\n\n#### The 3-step PCBA upload workflow (avoids rejection)\n\nJLCPCB's PCBA web upload rejects orders when the CPL contains designators\nthat aren't in the BOM (mechanical holes, fiducials, test points, etc.\nthat appear in the CPL output but aren't assembly components). The\ntranslator's `--bom` filter mode solves this:\n\n1. **Translate the BOM first** — produces the JLCPCB-format BOM and\n   establishes the authoritative designator set:\n   ```bash\n   python3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py bom input_bom.csv -o jlc_bom.csv\n   ```\n\n2. **Translate the CPL with `--bom` filter** — intersects CPL designators\n   with BOM designators, dropping orphans:\n   ```bash\n   python3 \u003Cbom-skill-path>\u002Fscripts\u002Ftranslate_bom_pnp.py pnp input_cpl.csv -o jlc_cpl.csv --units \u003Cin|mm> --bom jlc_bom.csv\n   ```\n   The returned `filtered_orphans` count plus `filtered_orphan_samples`\n   list lets the operator confirm which CPL rows were dropped — sanity-\n   check this list before uploading. Common orphans (mounting holes,\n   fiducials, test points) are expected; anything else may indicate a\n   BOM\u002FPCB mismatch worth investigating.\n\n3. **Tabulate consigned-parts cost separately** — JLCPCB's quote does\n   not auto-itemize consigned (user-supplied) part costs. Build a quote\n   summary that shows: PCB fabrication, PCBA assembly fee, basic vs\n   extended parts cost (per JLCPCB invoice), and a separate\n   user-sourced parts subtotal. Without this breakdown the quote\n   understates true unit cost by the consigned-parts amount.\n\nThis workflow is documented because JLCPCB's web upload UX silently\nrejects orphan-designator CPLs with an unhelpful error; the parity\ncheck via `--bom` is the single highest-value step in shipping a\nclean PCBA order.\n\n## Tips\n\n- **Prefer Basic parts** — no extra fee, always in stock, faster assembly\n- **Check stock before ordering** — extended parts can go out of stock; use the `lcsc` skill to search\n- **Panel by JLCPCB** — for small boards, let JLCPCB panelize (cheaper) vs custom panels\n- **Lead-free solder** — default is leaded (HASL); select lead-free HASL or ENIG if needed\n- **Impedance control** — available for multi-layer boards, specify stackup in order notes\n- **Castellated holes** — supported, enable in order options\n- **V-cuts and mouse bites** — supported for panel separation\n- **Silkscreen minimum** — 0.8mm height, 0.15mm line width for readable text\n- **Edge clearance** — keep copper >=0.3mm from board edge (0.5mm recommended)\n",{"name":5,"description":7},"main","47790c5af225ba335e83c027413077333397539e","plugins\u002Faklofas\u002Fkicad-happy\u002Fskills\u002Fjlcpcb",483,"https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins","https:\u002F\u002Fhol.org\u002Fplugins\u002Fbest-codex-plugins","https:\u002F\u002Fgithub.com\u002Fhashgraph-online","https:\u002F\u002Fhol.org","Open-source standards and developer tools for interoperable AI agents: discovery, identity, communication, payments, privacy and security.","2026-11-13 02:16:32",{"source":8,"skillName":5,"commands":63,"prompt":73,"zipAvailable":74},[64,67,70],{"tool":65,"command":66},"npx","npx skills add hashgraph-online\u002Fawesome-codex-plugins --skill jlcpcb",{"tool":68,"command":69},"bunx","bunx skills add hashgraph-online\u002Fawesome-codex-plugins --skill jlcpcb",{"tool":71,"command":72},"pnpm","pnpm dlx skills add hashgraph-online\u002Fawesome-codex-plugins --skill jlcpcb","安装技能，技能地址：https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Faklofas\u002Fkicad-happy\u002Fskills\u002Fjlcpcb\u002FSKILL.md",true,[],[77,85,92,99,124,147],{"skillNo":78,"name":79,"nameZh":6,"description":80,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":81,"categories":82,"keywords":83,"publishedAt":84},"01M746ZWACVKMZ1BJXJZHYJSSX","migrate-to-e2e","Moves an existing Playwright, Cypress, Selenium, Appium, Detox, Maestro, or TesterArmy suite to e2e one slice at a time, with the old suite running beside the new one until each ported test is proven. Keeps a MIGRATION.md progress file so any later session resumes where the last stopped. Optionally plants a defect to show both suites catch it. Use for \u002Fmigrate-to-e2e, \"migrate our tests to e2e\", \"port these Maestro flows\", \"move our TesterArmy tests\", or when a project has an e2e config and an older suite still running.","https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Ftester-army\u002Fe2e\u002Fskills\u002Fmigrate-to-e2e\u002FSKILL.md",[],[],"2026-11-11 15:11:14",{"skillNo":86,"name":87,"nameZh":6,"description":88,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":89,"categories":90,"keywords":91,"publishedAt":84},"01M746ZPTAX1Q0FBKAB1CYND7E","e2e","Writes, runs, and debugs end-to-end tests for web and mobile apps with e2e, the agentic test runner, which mixes agent.act goals with exact locator assertions on a Playwright browser or an iOS or Android device. Also drives a project's running app live over the e2e MCP server to look at a screen, check a UI change, take a screenshot or record a video, and try a locator; and runs bug bashes, parallel e2e explore runs with each bug proven by a repro test. Use when a project depends on e2e or has an e2e.config.ts, when asked for end-to-end, browser, mobile, or agentic UI tests, to check a change in the running app, to QA or bug bash an app or branch, or when an e2e run fails.","https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Ftester-army\u002Fe2e\u002Fskills\u002Fe2e\u002FSKILL.md",[],[],{"skillNo":93,"name":94,"nameZh":6,"description":95,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":96,"categories":97,"keywords":98,"publishedAt":84},"01M746ZJN784HVHMDP9MQGCSGG","create-verification-skill","Generate a project-local verify-\u003Capp> skill on top of e2e, so any coding agent can launch the app, check it is worth driving, exercise a feature the way a user does, keep evidence, and bug bash it. Writes the skill, a feature map with one explore charter per feature, and proves it once. Use for \u002Fcreate-verification-skill, \"make a verification skill for this repo\", or when a project has no scripted way to prove UI behavior.","https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Ftester-army\u002Fe2e\u002Fskills\u002Fcreate-verification-skill\u002FSKILL.md",[],[],{"skillNo":100,"name":101,"nameZh":6,"description":102,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":103,"categories":104,"keywords":105,"publishedAt":47},"01M716A6ETNB9B1SQ3GXZC75VR","deja-search","deja-vu memory — search the user's past AI coding sessions with the deja CLI. Holds what they already settled and never wrote into the repo (naming rules, banned or already-tried tools, required checks before merge, preferred values, who owns what). Use before your first edit in a task, before you call a change done or ready to merge, before you recommend a tool, library, design or reviewer, before re-debugging an error that may already be solved, when they say 'didn't we fix this before', 'what did we decide about X' or 'I already have that', and before telling them something on this machine does not exist.","https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Fvshulcz\u002Fdeja-vu\u002Fskills\u002Fdeja-search\u002FSKILL.md",[],[106,107,108,109,110,111,112,113,114,46,115,29,116,117,118,119,120,121,122,123],"search","deja search","never","error","ready","memory","re","decide","fix","debugging","you","done","reviewer","io","change","cli","merge","past",{"skillNo":125,"name":126,"nameZh":6,"description":127,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":128,"categories":129,"keywords":130,"publishedAt":47},"01M716A3J2W5SENSE9VGMXB375","deja-reflect","End-of-session reflection and memory curation with deja-vu. Review what was decided, what commands broke and what repaired them, and record durable project rules or decisions with deja remember so the next session starts with them.","https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Fvshulcz\u002Fdeja-vu\u002Fskills\u002Fdeja-reflect\u002FSKILL.md",[],[131,132,133,119,33,134,135,136,137,138,34,139,140,141,111,142,143,144,145,146],"deja reflect","reflect","review","record","github","next","https","node","decisions","brew","remember","project rules","project","session","end","reflection",{"skillNo":148,"name":149,"nameZh":6,"description":150,"descriptionZh":6,"repositoryFullName":8,"ownerLogin":9,"ownerAvatarUrl":10,"ownerAccountNo":11,"ownerDisplayName":12,"repositoryNo":13,"starsCount":14,"licenseSpdxId":15,"licenseFileUrl":6,"sourceHtmlUrl":151,"categories":152,"keywords":160,"publishedAt":47},"01M715T3RR4BAYSR57HPPTJ0PF","revid","Make, edit, export and post AI videos with Revid (revid.ai) through the Revid MCP server. Use whenever the user wants a short-form or long-form video made (from an idea, a script, a URL, an article, a PDF, a tweet, a product page, their own clips, or a song), wants to find what is going viral on TikTok, YouTube, Instagram or X before making something, wants to edit or re-export an existing Revid project, generate a standalone AI image or clip, make a series episode, or publish and schedule a finished video to connected social accounts. Covers setup (hosted MCP with OAuth, or an API key), the 36 tools, credits, polling and the rules for publishing. Routes to the more specific revid-* skills when one fits.","https:\u002F\u002Fgithub.com\u002Fhashgraph-online\u002Fawesome-codex-plugins\u002Fblob\u002Fmain\u002Fplugins\u002Ftmakersas\u002Frevid-skills\u002Fskills\u002Frevid\u002FSKILL.md",[153,156,157],{"categoryNo":154,"categoryName":155,"taxonomyType":21,"taxonomyTypeDesc":22},"01JBSEEDCAT000000000000016","图像与多媒体",{"categoryNo":24,"categoryName":25,"taxonomyType":21,"taxonomyTypeDesc":22},{"categoryNo":158,"categoryName":159,"taxonomyType":21,"taxonomyTypeDesc":22},"01JBSEEDCAT000000000000010","后端与接口",[149,161,162,163,164,165,166,143,167,112,168,169,170,171,29,172,173,174,175,176],"URL","Video","short-form","standalone","PDF","viral","tiktok","short","social","MCP","song","image","mcp server","schedule","api","publish"]